A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
A review on CMOS delay lines with a focus on the most frequently used techniques for high-
resolution delay step is presented. The primary types, specifications, delay circuits, and …
resolution delay step is presented. The primary types, specifications, delay circuits, and …
A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection …
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
A wide-range, high-resolution, compact, CMOS time to digital converter
V Ramakrishnan, PT Balsara - … on VLSI Design held jointly with …, 2006 - ieeexplore.ieee.org
This paper describes a wide range, area efficient, high resolution time to digital converter
(TDC), which has applications in digital frequency synthesizers used in wireless …
(TDC), which has applications in digital frequency synthesizers used in wireless …
An ultra-low-power and portable digitally controlled oscillator for SoC applications
In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based
design for system-on-chip (SoC) applications is presented. Based on the proposed …
design for system-on-chip (SoC) applications is presented. Based on the proposed …
Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL
This letter presents a 16-nm 496-core RISC-V network-onchip (NoC). The mesh achieves
1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a …
1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a …
A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm
CT Wu, WC Shen, W Wang… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked
loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the …
loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the …
Glitch-free NAND-based digitally controlled delay-lines
D De Caro - IEEE Transactions on Very Large Scale Integration …, 2012 - ieeexplore.ieee.org
The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a
glitching problem which may limit their employ in many applications. This paper presents a …
glitching problem which may limit their employ in many applications. This paper presents a …
Parameterized all-digital PLL architecture and its compiler to support easy process migration
CW Tzeng, SY Huang, PY Chao - IEEE Transactions on Very …, 2013 - ieeexplore.ieee.org
In this paper, we propose a parameterized digitally controlled oscillator that can produce
oscillating-clock signal with the tunable frequency covering an entire designated range …
oscillating-clock signal with the tunable frequency covering an entire designated range …
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
This work presents a clock generator with cascaded dynamic frequency counting (DFC)
loops for wide multiplication range applications. The DFC loop, which uses variable time …
loops for wide multiplication range applications. The DFC loop, which uses variable time …
A fast locking all-digital phase-locked loop via feed-forward compensation technique
X Chen, J Yang, LX Shi - … on very large scale integration (VLSI) …, 2010 - ieeexplore.ieee.org
A fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation
technique is proposed in this paper. The implemented ADPLL has two operation modes …
technique is proposed in this paper. The implemented ADPLL has two operation modes …