VLSI implementation of fully parallel LTE turbo decoders
Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable
iterative forward error correction. However, owing to the serial data dependence imposed by …
iterative forward error correction. However, owing to the serial data dependence imposed by …
1.5 Gbit/s FPGA implementation of a fully-parallel turbo decoder designed for mission-critical machine-type communication applications
In wireless communication schemes, turbo codes facilitate near-capacity transmission
throughputs by achieving reliable forward error correction. However, owing to the serial data …
throughputs by achieving reliable forward error correction. However, owing to the serial data …
A scalable system architecture for high-throughput turbo-decoders
MJ Thul, F Gilbert, T Vogt, G Kreiselmaier… - Journal of VLSI signal …, 2005 - Springer
The need for higher data rates is ever rising as wireless communications standards move
from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for …
from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for …
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
Standard VLSI implementations of turbo decoding require substantial memory and incur a
long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for …
long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for …
Selection of channel coding for low-power wireless systems
C Desset, A Fort - The 57th IEEE Semiannual Vehicular …, 2003 - ieeexplore.ieee.org
The wireless communications world is moving towards the so-called 4G pictures, by
integrating many different subsystems. Some of them have to provide short-range …
integrating many different subsystems. Some of them have to provide short-range …
A parametrizable low-power high-throughput turbo-decoder
G Prescher, T Gemmeke, TG Noll - Proceedings.(ICASSP'05) …, 2005 - ieeexplore.ieee.org
The paper presents a high performance turbo decoder. Its major building blocks, the
maximum-a-posteriori decoder and the interleaver, are optimized from architecture to layout …
maximum-a-posteriori decoder and the interleaver, are optimized from architecture to layout …
[图书][B] Turbo codes: Desirable and designable
A Giulietti, B Bougard, L Van Der Perre - 2003 - books.google.com
PREFACE The increasing demand on high data rate and quality of service in wireless
communication has to cope with limited bandwidth and energy resources. More than 50 …
communication has to cope with limited bandwidth and energy resources. More than 50 …
A class of power efficient VLSI architectures for high speed turbo-decoding
B Bougard, A Giulietti, L Van der Perre… - … 2002. GLOBECOM'02 …, 2002 - ieeexplore.ieee.org
Turbo codes have become an attractive forward error correction scheme for broadband
communications, providing near optimal coding gain. However, the limited throughput, the …
communications, providing near optimal coding gain. However, the limited throughput, the …
VLSI architectural design tradeoffs for sliding-window log-MAP decoders
Turbo codes have received tremendous attention and have commenced their practical
applications due to their excellent error-correcting capability. Investigation of efficient …
applications due to their excellent error-correcting capability. Investigation of efficient …
Design of Low-Power Turbo Coder for Low-Energy Mobile Communications
Mobile Communication systems use turbo codes for correcting errors. As compared to other
error correction codes, turbo codes provide great error correcting capabilities. The design of …
error correction codes, turbo codes provide great error correcting capabilities. The design of …