Compute-in-memory chips for deep learning: Recent trends and prospects

S Yu, H Jiang, S Huang, X Peng… - IEEE circuits and systems …, 2021 - ieeexplore.ieee.org
Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall
problem in hardware accelerator design for deep learning. The input vector and weight …

Drisa: A dram-based reconfigurable in-situ accelerator

S Li, D Niu, KT Malladi, H Zheng, B Brennan… - Proceedings of the 50th …, 2017 - dl.acm.org
Data movement between the processing units and the memory in traditional von Neumann
architecture is creating the" memory wall" problem. To bridge the gap, two approaches, the …

Neurocube: A programmable digital neuromorphic architecture with high-density 3D memory

D Kim, J Kung, S Chai, S Yalamanchili… - ACM SIGARCH …, 2016 - dl.acm.org
This paper presents a programmable and scalable digital neuromorphic architecture based
on 3D high-density memory integrated with logic tier for efficient neural computing. The …

Haswell: The fourth-generation intel core processor

P Hammarlund, AJ Martinez, AA Bajwa, DL Hill… - IEEE micro, 2014 - ieeexplore.ieee.org
Haswell, Intel's fourth-generation core processor architecture, delivers a range of client
parts, a converged core for the client and server, and technologies used across many …

Haswell: A family of IA 22 nm processors

N Kurd, M Chowdhury, E Burton… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
We describe the 4th Generation Intel® Core™ processor family (codenamed “Haswell”)
implemented on Intel® 22 nm technology and intended to support form factors from desktops …

Scope: A stochastic computing engine for dram-based in-situ accelerator

S Li, AO Glova, X Hu, P Gu, D Niu… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Memory-centric architecture, which bridges the gap between compute and memory, is
considered as a promising solution to tackle the memory wall and the power wall. Such …

Review of chiplet-based design: system architecture and interconnection

Y Liu, X Li, S Yin - Science China Information Sciences, 2024 - Springer
Chiplet-based design, which breaks a system into multiple smaller dice (or “chiplets”) and
reassembles them into a new system chip through advanced packaging, has received …

T-PIM: An energy-efficient processing-in-memory accelerator for end-to-end on-device training

J Heo, J Kim, S Lim, W Han… - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
Recently, on-device training has become crucial for the success of edge intelligence.
However, frequent data movement between computing units and memory during training …

1.1 Moore's law: A path going forward

WM Holt - 2016 IEEE International Solid-State Circuits …, 2016 - ieeexplore.ieee.org
Semiconductors continue to be the foundation for computing and communications solutions,
the basis of the Internet of Everthing, and the primary driver in the future of electronics …

Ferroelectric hafnium zirconium oxide compatible with back-end-of-line process

J Hur, YC Luo, N Tasneem, AI Khan… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or
beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good …