[图书][B] CMOS time-mode circuits and systems: fundamentals and applications

F Yuan - 2018 - books.google.com
Time-mode circuits, where information is represented by time difference between digital
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …

A novel design methodology for high tuning linearity and wide tuning range ring voltage controlled oscillator

G Rajahari, YA Varshney, SC Bose - … , VDAT 2013, Jaipur, India, July 27-30 …, 2013 - Springer
This paper presents a novel design methodology of a CMOS current starved ring Voltage
Controlled Oscillator (VCO) for wide tuning range and high linearity. The fV tuning …

Ad converter

T Itakura, M Furuta, A Sai, J Matsuno - US Patent 9,136,855, 2015 - Google Patents
In one embodiment, an AD converter includes a first (second) oscillation circuit, a first
(second) counter, a first (second) arithmetic circuit, a first (second) subtracting circuit, an …

A 6-b, 800-MS/s, 3.62-mW Nyquist rate ac-coupled VCO-based ADC in 65-nm CMOS

M Hassanpourghadi, PK Sharma… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
A Nyquist voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC)
architecture is proposed for ac-coupled systems that are commonly used in high-speed …

VCO-based ADC with built-in supply noise immunity using injection-locked ring oscillators

KM Al-Tamimi, K El-Sankary… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs)
demonstrate superior hardware efficiency. They benefit from the technology scaling; …

An uncalibrated 2MHz, 6mW, 63.5 dB SNDR discrete-time input VCO-based ΔΣ ADC

J Hamilton, S Yan… - Proceedings of the IEEE …, 2012 - ieeexplore.ieee.org
A 63.5 dB, 2MHz bandwidth ΔΣ ADC using two ICOs pseudo-differentially as an
integrator/quantizer and a combined front-end switched-capacitor VI converter and feedback …

A 10MHz-BW, 5.6 mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM

K Lee, Y Yoon, N Sun - 2013 IEEE International Symposium on …, 2013 - ieeexplore.ieee.org
This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other
VCO based ADC, it does not contain operational amplifier which is power hungry and …

A PSRR enhancing method for GRO TDC based clock generation systems

Y Liu, Y Han, W Rhee, TY Oh… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper discusses a supply noise sensitivity problem of the gated ring oscillator (GRO)
based time-to-digital converter (TDC) in all-digital phase-locked loops (ADPLLs) and …

Design techniques for time-mode noise-shaping analog-to-digital converters: a state-of-the-art review

F Yuan - Analog Integrated Circuits and Signal Processing, 2014 - Springer
The paper provides a comprehensive treatment of time-mode noise-shaping analog-to-
digital converters (ADCs). An in-depth examination of the principle, advantages, and …

Design challenges for vco based adcs for ultra-low power operation

N Narasimman, TTH Kim - 2013 International SoC Design …, 2013 - ieeexplore.ieee.org
Quest for ultra-low power ADCs have forced researchers to push existing ADC architectures
to work in ultra-low voltage supply. VCO based ADCs are promising solutions to address this …