[图书][B] Reconfigurable computing: the theory and practice of FPGA-based computation
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …
between the separate worlds of hardware and software design—the key feature of …
Credibility in context: An analysis of feature distributions in twitter
J ODonovan, B Kang, G Meyer… - … on Privacy, Security …, 2012 - ieeexplore.ieee.org
Twitter is a major forum for rapid dissemination of user-provided content in real time. As
such, a large proportion of the information it contains is not particularly relevant to many …
such, a large proportion of the information it contains is not particularly relevant to many …
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication
Y Nakamura, K Hosokawa, I Kuroda… - Proceedings of the 41st …, 2004 - dl.acm.org
This paper describes a new hardware/software co-verification method for System-On-a-
Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator …
Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator …
Methodologies and tools for pipelined on-chip interconnect
L Scheffer - … Conference on Computer Design: VLSI in …, 2002 - ieeexplore.ieee.org
As processes shrink, gate delay improves much faster than the delay in long wires.
Therefore, the long wires increasingly determine the maximum clock rate, and hence …
Therefore, the long wires increasingly determine the maximum clock rate, and hence …
MC-Sim: An efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom
hardware blocks and complex network-on-chip (NoC) communication frameworks onto a …
hardware blocks and complex network-on-chip (NoC) communication frameworks onto a …
Re-use-centric architecture for a fully accelerated testbench environment
R Henftling, A Zinn, M Bauer, M Zambaldi… - Proceedings of the 40th …, 2003 - dl.acm.org
This paper presents a new technology that accelerates functional system verification.
Starting with a behavioral testbench, we developed a seamless flow to generate a re-use …
Starting with a behavioral testbench, we developed a seamless flow to generate a re-use …
An intrusive dynamic reconfigurable cycle-accurate debugging system for embedded processors
HH Khan, A Kamal, D Goehringer - … , ARC 2018, Santorini, Greece, May 2 …, 2018 - Springer
This paper presents a dynamic partial reconfigurable debugging system for embedded
processors based upon a device start and stop (DSAS) approach [1]. Using this approach, a …
processors based upon a device start and stop (DSAS) approach [1]. Using this approach, a …
Verification method and system for logic circuit
Y Nakamura - US Patent 7,395,197, 2008 - Google Patents
A shared register row is provided between a program-based circuit simulator and a device-
based circuit simulator. The shared register row includes a plurality of shared registers each …
based circuit simulator. The shared register row includes a plurality of shared registers each …
Hardware-assisted simulation and evaluation of IP cores using FPGA-based rapid prototyping boards
R Siripokarpirom… - Proceedings. 15th IEEE …, 2004 - ieeexplore.ieee.org
This paper presents a methodology for incorporating intellectual property (IP) cores that are
implemented with SRAM-based FPGA logic into an existing hardware simulation …
implemented with SRAM-based FPGA logic into an existing hardware simulation …
DSP instruction set simulation
An instruction set simulator is an important tool for system architects and for software
developers. However, when implementing a simulator, there are many choices which can be …
developers. However, when implementing a simulator, there are many choices which can be …