2005-08-05 Assigned to PACT XPP TECHNOLOGIES AG reassignment PACT XPP
TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

An internal bus system for DFPs and units with two-or multi-dimensional programmable cell
architectures, for managing large Volumes of data with a high interconnection complexity …

Today, most processors in microcomputer Systems pro vide a 64-bit wide datapath
architecture. The 64-bit datapath allows operations Such as read, write, add, Subtract, and …

An arrangement and a method are provided for replacing defective units, which can be any
desired unit of a chip (eg, arithmetic and logic units), with a function unit. The arrangement …

This invention provides a computer system architecture and method for providing the same
which can include a web page search node including a web page collection. The system …

To perform multiplication of matrices in a vector processing system, partial products are
obtained by dot multiplication of vector registers containing multiple copies of elements of a …

(57) ABSTRACT A cascadable arithmetic and logic unit (ALU) which is con figurable in
function and interconnection. No decoding of commands is needed during execution of the …

An object of the present invention is to reduce the expense of wiring, and in particular to
reduce the number of unit terminals. The present invention provides a uniform bus System …

(57) ABSTRACT A method for processing data in a configurable unit having a
multidimensional cell arrangement a Switching table is provided, the Switching table …

(57) ABSTRACT A data processing device comprising a multidimensional array of coarse
grained logic elements processing data and operating at a? rst clock rate and …