As the number of on-chip cores and memory demands of applications increase, judicious
management of cache resources has become not merely attractive but imperative. Cache …

This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

Shared last-level caches, widely used in chip-multi-processors (CMPs), face two
fundamental limitations. First, the latency and energy of shared caches degrade as the …

Caches are traditionally organized as a rigid hierarchy, with multiple levels of progressively
larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range …

A key determinant of overall system performance and power dissipation is the cache
hierarchy since access to off-chip memory consumes many more cycles and energy than on …

Cache hierarchies are increasingly non-uniform and difficult to manage. Several techniques,
such as scratchpads or reuse hints, use static information about how programs access data …

The number of cores in a single chip multiprocessor is expected to grow in coming years.
Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilization is …

The datacenter introduces new challenges for computer systems around tail latency and
security. This paper argues that dynamic NUCA techniques are a better solution to these …

Data-intensive applications put immense strain on the memory systems of Graphics
Processing Units (GPUs). To cater to this need, GPU memory systems distribute requests …

Wire energy has become the major contributor to energy in large lower level caches. While
wire energy is related to wire latency its costs are exposed differently in the memory …