Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number

D Datta, B Datta, HS Dutta - 2017 Devices for Integrated Circuit …, 2017 - ieeexplore.ieee.org
Pseudorandom number generators (PRNGs) are important role in cryptography application.
Hardware based random number generators become faster. Field Programming Gate Arrays …

Design and analysis of low-transition address generator

S Saravanan, M Hailu, GM Gouse, M Lavanya… - Advances of Science …, 2019 - Springer
In high-speed Nano-scale VLSI designs, memory plays a vital role of operation. Built-In Self-
Test (BIST) for memory is an essential element of the system-on-chip (SoC). Investigating …

Low power memory built in self test address generator using clock controlled linear feedback shift registers

KM Krishna, M Sailaja - Journal of Electronic Testing, 2014 - Springer
In the ongoing high-speed, high-tech sophistication in the technology of VLSI designs, Built-
in Self-Test (BIST) is emerging as the essential element of the memory, which can be treated …

[PDF][PDF] Design and analysis of low power memory built in self test architecture for SoC based design

S Vennelakanti, S Saravanan - Indian Journal …, 2015 - sciresol.s3.us-east-2.amazonaws …
This paper targets on the low power design of Memory Built In Self Test (MBIST) architecture
for System on Chip (SoC) based design. Proposed address generator is developed with the …

[PDF][PDF] FPGA implementation of an LFSR based pseudorandom pattern generator for mems testing

MF Islam, MAM Ali, BY Majlis - International Journal of Computer …, 2013 - Citeseer
Recent strides in programmable logic density, speed and hardware description language
(HDL) have empowered the engineer with the ability to implement high-performance digital …

Design of test generator for embedded self-testing

S Rodzin - 2015 IEEE East-West Design & Test Symposium …, 2015 - ieeexplore.ieee.org
The authors consider the built-in self-test signature model. This article describes the analysis
shows the ability of signature schemes, as well as the synthesis of the test generator. The …

[PDF][PDF] Strategies and Techniques for Optimizing Power in BIST: A Review

A Singh, PM Kumar, M Bassi - International Journal of Computer …, 2014 - Citeseer
Power dissipation is a challenging problem in current VLSI designs. In general the power
consumption of device is more in the testing mode than in the normal system operation. Built …

[PDF][PDF] Low power Hybrid CA register design for BIST applications

A Singh, PM Kumar - researchgate.net
With the increasing complexity and operation frequencies of Very Large Scale Integration
(VLSI) circuit designs, the power dissipation of VLSI circuits is rapidly increasing, causing …