The present invention generally relates to a memory device including a delay locked loop
(hereinafter, referred to as “DLL), and more specifically, to a memory device including a DLL …

There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an
EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a …

BACKGROUND Modern high-speed integrated circuit devices, such as Syn chronous
dynamic random access memories (SDRAM), microprocessors, etc., rely upon clock signals …

(57) ABSTRACT A delay amount variable circuit (8) adapted to change a delay amount
according to a ZO calibration result is inserted in a path of a DQ replica system. The delay …

In a data output circuit, a data output method, and a semiconductor memory device, the data
output circuit includes: an internal clock generation unit that delays an external clock signal …

(57) ABSTRACT A phase mixer includes a phase mixing unit configured to mix a phase of a
first input signal and a phase of a second input signal in response to a phase control signal …

0004 2. Description of the Related Art 0005. In synchronous semiconductor memory
devices, operations are performed in Synchronization with a refer ence clock signal. In …

In a method of training for a memory device, an initialization operation is performed on the
memory device when the memory device is powered on. A training operation is performed …

A semiconductor device includes a delay locked loop includ ing a replica delay unit which is
configured to delay a signal reflecting a delay amount of an output path of a signal, and a …

BACKGROUND Modern high-speed integrated circuit devices, such as Syn chronous
dynamic random access memories (SDRAM), microprocessors, etc., rely upon clock signals …