A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches

S Mittal, JS Vetter, D Li - IEEE Transactions on Parallel and …, 2014 - ieeexplore.ieee.org
Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …

The new hardware development trend and the challenges in data management and analysis

W Pan, Z Li, Y Zhang, C Weng - Data Science and Engineering, 2018 - Springer
Hardware techniques and environments underwent significant transformations in the field of
information technology, represented by high-performance processors and hardware …

Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems

Q Li, J Li, L Shi, M Zhao, CJ Xue… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
Hybrid caches consisting of static RAM (SRAM) and spin-torque transfer (STT)-RAM have
been proposed recently for energy efficiency. To explore the advantages of hybrid cache …

3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems

C Pan, M Xie, J Hu, Y Chen, C Yang - Proceedings of the 2014 …, 2014 - dl.acm.org
Multi-level Cell (MLC) Phase Change Memory (PCM) has many attractive features to be
used as main memory for embedded systems. These features include low power, high …

Volatile STT-RAM scratchpad design and data allocation for low energy

G Rodríguez, J Touriño, MT Kandemir - ACM Transactions on …, 2014 - dl.acm.org
On-chip power consumption is one of the fundamental challenges of current technology
scaling. Cache memories consume a sizable part of this power, particularly due to leakage …

Exploiting multiple write modes of nonvolatile main memory in embedded systems

C Pan, M Xie, C Yang, Y Chen, J Hu - ACM Transactions on Embedded …, 2017 - dl.acm.org
Existing Nonvolatile Memories (NVMs) have many attractive features to be the main memory
of embedded systems. These features include low power, high density, and better …

Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration

WK Cheng, YH Ciou, PY Shen - Microprocessors and Microsystems, 2016 - Elsevier
Abstract Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and
ignorable leakage power. However, it suffers from the bad write latency and poor write …

Architecting the last-level cache for GPUs using STT-RAM technology

MH Samavatian, M Arjomand, R Bashizade… - ACM Transactions on …, 2015 - dl.acm.org
Future GPUs should have larger L2 caches based on the current trends in VLSI technology
and GPU architectures toward increase of processing core count. Larger L2 caches …

MH cache: A multi-retention STT-RAM-based low-power last-level cache for mobile hardware rendering systems

J Park, M Lee, S Kim, M Ju, J Hong - ACM Transactions on Architecture …, 2019 - dl.acm.org
Mobile devices have become the most important devices in our life. However, they are
limited in battery capacity. Therefore, low-power computing is crucial for their long lifetime. A …

Fine grained, direct access file system support for storage class memory

Y Wang, T Wang, D Liu, Z Shao, J Xue - Journal of Systems Architecture, 2017 - Elsevier
New storage class memory (SCM) technologies, such as phase change memory (PCM) and
memristors, are not only byte-addressable like DRAM but also non-volatile like traditional …