With the increasing complexity of IC products, large-scale designs must be efficiently
partitioned into multiple blocks, tiles, or devices for concurrent backend place-and-route …

Timing optimization is critical to integrated circuit (IC) design closure. Existing global
placement algorithms mostly focus on wirelength optimization without considering timing. In …

Optimizing timing is critical to the design closure of integrated circuits (ICs). However, most
existing algorithms for circuit placement focus on the optimization of wirelength instead of …

Despite the recent progress on machine learning (ML) based performance modeling, two
major concerns that may impede production-ready ML applications in electronic design …

State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes
and aggressive bonding pitch assumptions. As a result, these flows fail to honor the width …

In physical design, human designers typically place macros via trial and error, which is a
Markov decision process. Reinforcement learning (RL) methods have demonstrated …

This paper presents a physical mapping tool for quantum circuits, which generates the
optimal universal logic block (ULB) that can, on average, perform any logical fault-tolerant …

Asynchronous circuits offer promise in handling current and future technology scaling
challenges. Unfortunately, their impact has been limited by the lack of design automation …

In this paper, we propose a 2-dimensional dynamic programming (DP) based detailed
placement algorithm for modern FPGAs for wirelength and timing optimization. By tuning a …

In this paper, we propose Lagrangian relaxation (LR)-based algorithms to optimize both
circuit performance and total wirelength at the global placement stage. We introduce a …