Hierarchical scheduling framework for virtual clustering of multiprocessors
Scheduling of sporadic task systems on multiprocessor platforms is an area which has
received much attention in the recent past. It is widely believed that finding an optimal …
received much attention in the recent past. It is widely believed that finding an optimal …
Benchmarking for large-scale placement and beyond
Over the last five years the VLSI Placement community achieved great strides in the
understanding of placement problems, developed new high-performance algorithms, and …
understanding of placement problems, developed new high-performance algorithms, and …
Accurate pseudo-constructive wirelength and congestion estimation
AB Kahng, X Xu - Proceedings of the 2003 international workshop on …, 2003 - dl.acm.org
Accurate estimation of wirelength and congestion is one of the fundamental issues in VLSI
physical design. Current probabilistic estimation methods fail to produce accurate results …
physical design. Current probabilistic estimation methods fail to produce accurate results …
Provision of security in vehicular ad hoc networks through an intelligent secure routing scheme
KN Qureshi, F Bashir… - … international conference on …, 2017 - ieeexplore.ieee.org
Vehicular Ad hoc Networks (VANETs) are providing road management systems by a wide
variety of different value-added safety and infotainment applications. The main aim of these …
variety of different value-added safety and infotainment applications. The main aim of these …
Binary synthesis
Recent high-level synthesis approaches and C-based hardware description languages
attempt to improve the hardware design process by allowing developers to capture desired …
attempt to improve the hardware design process by allowing developers to capture desired …
Capacity-constrained network-voronoi diagram
Given a graph and a set of service center nodes, a Capacity Constrained Network-Voronoi
Diagram (CCNVD) partitions the graph into a set of contiguous service areas that meet …
Diagram (CCNVD) partitions the graph into a set of contiguous service areas that meet …
Compile-time area estimation for LUT-based FPGAs
The Cameron Project has developed a system for compiling codes written in a high-level
language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit …
language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit …
A-priori wirelength and interconnect estimation based on circuit characteristics
S Balachandran, D Bhatia - … of the 2003 international workshop on …, 2003 - dl.acm.org
Interconnect prediction is very important for early feasibility studies in modern design flows.
Most of the interconnect estimation techniques estimate average or total wirelength and …
Most of the interconnect estimation techniques estimate average or total wirelength and …
Congestion estimation and localization in FPGAs: a visual tool for interconnect prediction
D Yeager, D Chiu, G Lemieux - … of the 2007 international workshop on …, 2007 - dl.acm.org
In this paper, we are concerned with locating the most congested regions in FPGA designs
before routing is completed. As well, we are interested in the amount of congestion in these …
before routing is completed. As well, we are interested in the amount of congestion in these …
Interconnect estimation for FPGAs
P Kannan, D Bhatia - … on Computer-Aided Design of Integrated …, 2006 - ieeexplore.ieee.org
Interconnect planning is becoming an important design issue for large field programmable
gate array (FPGA)-based designs. One of the most important issues for planning …
gate array (FPGA)-based designs. One of the most important issues for planning …