This article introduces a novel approach of hybrid current-starved ring voltage-controlled
oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high …

Delay locked loop is a critical building block of high speed synchronous circuits. An
improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this …

A low-jitter charge-pumped phase-locked loop (CPPLL) with four-stage differential delay
units is implemented in 180 nm standard CMOS technology. Not only a current-steering …

This paper reviews the design of phase locked loop (PLL) using recently reported charge
pump circuits. Lock time, phase noise, lock range and reference spur of each charge pump …

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring
type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is …

In this paper, a specific circuit topology called NMOS-Switch Current Steering Charge Pump
is presented. The circuit is designed using a 65nm CMOS Technology process. The main …

Phase-Locked Loops have a wide range of applications as frequency synthesizers. An
analysis of Integer-N Phase-Locked-Loop (PLL) is presented in this article. The performance …

Digital Phase locked loop (DPLL) is one of the most important devices in almost all the
electronic systems. This paper introduces the design of DPLL using sub-micron 45nm …

This paper proposes design and implementation of low power Delay Locked Loop
Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum …

This paper presents a Phase Locked Loop (PLL) which works with minimum jitter in the
operation frequency range of 600MHZ to 900MHZ. Utilizing a full differential architecture that …