Formal verification utilizing symbolic computer algebra has demonstrated the ability to formally verify large Galois field arithmetic circuits and basic architectures of integer …
Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry today. The possibility of hardware …
A Mahzoon, D Große… - 2018 IEEE/ACM …, 2018 - ieeexplore.ieee.org
Nowadays, a variety of multipliers are used in different computationally intensive industrial applications. Most of these multipliers are highly parallelized and structurally complex …
A Mahzoon, D Große… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The formal verification of integer multipliers is one of the important but challenging problems in the verification community. Recently, the methods based on symbolic computer algebra …
C Yu, M Ciesielski, A Mishchenko - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Constructing algebraic polynomials using computer algebra techniques is believed to be state-of-the-art in analyzing gate-level arithmetic circuits. However, the existing approach …
A Mahzoon, D Große, C Scholl… - … Design, Automation & …, 2020 - ieeexplore.ieee.org
Formal verification methods have made huge progress over the last decades. However, proving the correctness of arithmetic circuits involving integer multipliers still drives the …
F Farahmandi, Y Huang… - 2017 22nd Asia and South …, 2017 - ieeexplore.ieee.org
Growing reliance on reusable hardware Intellectual Property (IP) blocks, severely affects the security and trustworthiness of System-on-Chips (SoCs) since untrusted third-party vendors …
Verifying the functional correctness of a circuit is often the most time-consuming part of the design process. Recently, world-level formal verification methods, eg, Binary Moment …
In recent years, significant effort has been put into developing formal verification approaches by both academic and industrial research. In practice, these techniques often give satisfying …