RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers

A Mahzoon, D Große, R Drechsler - Proceedings of the 56th Annual …, 2019 - dl.acm.org
In recent years, formal methods based on Symbolic Computer Algebra (SCA) have shown
very good results in verification of integer multipliers. The success is based on removing …

Formal verification of integer multipliers by combining Gröbner basis with logic reduction

A Sayed-Ahmed, D Große, U Kühne… - … , Automation & Test …, 2016 - ieeexplore.ieee.org
Formal verification utilizing symbolic computer algebra has demonstrated the ability to
formally verify large Galois field arithmetic circuits and basic architectures of integer …

Pre-silicon security verification and validation: A formal perspective

X Guo, RG Dutta, Y Jin, F Farahmandi… - Proceedings of the 52nd …, 2015 - dl.acm.org
Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has
emerged as a pervasive design practice in the industry today. The possibility of hardware …

PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers

A Mahzoon, D Große… - 2018 IEEE/ACM …, 2018 - ieeexplore.ieee.org
Nowadays, a variety of multipliers are used in different computationally intensive industrial
applications. Most of these multipliers are highly parallelized and structurally complex …

RevSCA-2.0: SCA-based formal verification of nontrivial multipliers using reverse engineering and local vanishing removal

A Mahzoon, D Große… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The formal verification of integer multipliers is one of the important but challenging problems
in the verification community. Recently, the methods based on symbolic computer algebra …

Fast algebraic rewriting based on and-inverter graphs

C Yu, M Ciesielski, A Mishchenko - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Constructing algebraic polynomials using computer algebra techniques is believed to be
state-of-the-art in analyzing gate-level arithmetic circuits. However, the existing approach …

Towards formal verification of optimized and industrial multipliers

A Mahzoon, D Große, C Scholl… - … Design, Automation & …, 2020 - ieeexplore.ieee.org
Formal verification methods have made huge progress over the last decades. However,
proving the correctness of arithmetic circuits involving integer multipliers still drives the …

Trojan localization using symbolic algebra

F Farahmandi, Y Huang… - 2017 22nd Asia and South …, 2017 - ieeexplore.ieee.org
Growing reliance on reusable hardware Intellectual Property (IP) blocks, severely affects the
security and trustworthiness of System-on-Chips (SoCs) since untrusted third-party vendors …

Polynomial word-level verification of arithmetic circuits

M Barhoush, A Mahzoon, R Drechsler - Proceedings of the 19th ACM …, 2021 - dl.acm.org
Verifying the functional correctness of a circuit is often the most time-consuming part of the
design process. Recently, world-level formal verification methods, eg, Binary Moment …

Polynomial Formal Verification of Arithmetic Circuits

A Mahzoon, R Drechsler - Foundations and Trends® in …, 2024 - nowpublishers.com
In recent years, significant effort has been put into developing formal verification approaches
by both academic and industrial research. In practice, these techniques often give satisfying …