Modifying the Power and Performance of 2-Dimensional MoS2 Field Effect Transistors
Over the past 60 years, the semiconductor industry has been the core driver for the
development of information technology, contributing to the birth of integrated circuits …
development of information technology, contributing to the birth of integrated circuits …
Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Subthreshold behavior
We present a detailed TCAD analysis of the impact of length scaling and the associated
short-channel effects in the subthreshold regime of the two classes of double-gate negative …
short-channel effects in the subthreshold regime of the two classes of double-gate negative …
Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation
C Fiegna, Y Yang, E Sangiorgi… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS
technology and applies device simulation to analyze the impact of thermal effects on the …
technology and applies device simulation to analyze the impact of thermal effects on the …
Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain
P Palestri, D Esseni, S Eminente… - … on Electron Devices, 2005 - ieeexplore.ieee.org
In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to
the potential and calibrated scattering models are used to study electronic transport in bulk …
the potential and calibrated scattering models are used to study electronic transport in bulk …
Experimental study on carrier transport mechanisms in double-and single-gate ultrathin-body MOSFETs-Coulomb scattering, volume inversion, and/spl delta/T/sub …
The carrier transport mechanisms in single-and double-gate UTB MOSFETs are
investigated. It is demonstrated that Coulomb scattering in UTB MOSFETs is greater than …
investigated. It is demonstrated that Coulomb scattering in UTB MOSFETs is greater than …
On the modeling of surface roughness limited mobility in SOI MOSFETs and its correlation to the transistor effective field
D Esseni - IEEE Transactions on Electron Devices, 2004 - ieeexplore.ieee.org
In this paper, we discuss in detail the modeling of surface roughness (SR) scattering in
single-and double-gate silicon-on-insulator (SOI) MOSFETs, where the conventional …
single-and double-gate silicon-on-insulator (SOI) MOSFETs, where the conventional …
Low-field electron mobility model for ultrathin-body SOI and double-gate MOSFETs with extremely small silicon thicknesses
A number of experiments have recently appeared in the literature that extensively
investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body …
investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body …
A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain
We have performed a simulation study of symmetric ultrathin-body double-gate (SUTBDG)
devices with metal source/drain (S/D) structures designed for low-operating-power …
devices with metal source/drain (S/D) structures designed for low-operating-power …
Improving bulk FinFET DC performance in comparison to SOI FinFET
The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-
cost technology and compatibility with standard bulk CMOS in comparison with silicon-on …
cost technology and compatibility with standard bulk CMOS in comparison with silicon-on …
Mobility enhancement by back-gate biasing in ultrathin SOI MOSFETs with thin BOX
A Ohata, Y Bae, C Fenouillet-Beranger… - IEEE Electron …, 2012 - ieeexplore.ieee.org
Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm)
SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ …
SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ …