Study of temperature effect on analog/RF and linearity performance of dual material gate (DMG) vertical super-thin body (VSTB) FET
This work presents a simulation study of the influence of temperature on the performance of
dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG …
dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG …
Methods to Improve Linearity of Signal's Analog-to-Digital Conversion with Self-Calibration
V Melikyan - Machine Learning-based Design and Optimization of …, 2023 - Springer
This chapter is devoted to the development of embedded methods for ADCs and DACs,
which will allow to reduce the impact of errors after manufacturing process through self …
which will allow to reduce the impact of errors after manufacturing process through self …
[图书][B] Machine Learning-based Design and Optimization of High-Speed Circuits
V Melikyan - 2024 - Springer
The book systematically expounds the main results obtained by the author in the field of
design and optimization of high-speed integrated circuits (ICs) and their standard blocks …
design and optimization of high-speed integrated circuits (ICs) and their standard blocks …
[PDF][PDF] A Dynamic Supply Modulator in 18 nm FinFET Node Using Comparator Approach
S Gangadharan, R Khanam, V Thangasamy - Int. J. Exp. Res. Rev, 2024 - academia.edu
To keep up with the rapid development and to increase spectral efficiency, emerging
communication systems like 5G will need to transfer data at speeds significantly faster than …
communication systems like 5G will need to transfer data at speeds significantly faster than …
Design of high speed dynamic comparator in 28nm cmos
Y Cao, C Zhang - 2018 IEEE Asia Pacific Conference on …, 2018 - ieeexplore.ieee.org
This paper presents a high-speed dynamic comparator which could optimize the basically
differential amplifier and class AB latch circuit, designed and verified in UMC 28nm CMOS …
differential amplifier and class AB latch circuit, designed and verified in UMC 28nm CMOS …
[PDF][PDF] Design and Simulation of Comparator Architectures for Various ADC Applications
D Gaude, B Poornima, KM Sudharshan, PV Joshi - 2019 - academia.edu
This paper presents design and simulation of different CMOS comparators. The designs are
simulated and studied in 180 nm Technology with Cadence Virtuoso Tool with supply …
simulated and studied in 180 nm Technology with Cadence Virtuoso Tool with supply …
[PDF][PDF] Educational background
J Sunsuria, B Sunsuria - solar cells, 2023 - xmum.my
Curriculum Vitae for XMUM Official Website BIOGRAPHY RESEARCH INTERESTS
EDUCATIONAL BACKGROUND Page 1 Curriculum Vitae for XMUM Official Website Name Dr …
EDUCATIONAL BACKGROUND Page 1 Curriculum Vitae for XMUM Official Website Name Dr …