A 64 Gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS
E Depaoli, H Zhang, M Mazzini… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A four-level pulse-amplitude modulation (PAM-4) transceiver operating up to 64 Gb/s in 28-
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …
A review on calibration methods of timing-skew in time-interleaved ADCs
X Li, C Huang, D Ding, J Wu - Journal of Circuits, Systems and …, 2020 - World Scientific
Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters
(ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain …
(ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain …
[图书][B] Developing digital RF memories and transceiver technologies for electromagnetic warfare
PE Pace - 2022 - books.google.com
This book provides a comprehensive resource and thorough treatment in the latest
development of Digital RF Memory (DRFM) technology and their key role in maintaining …
development of Digital RF Memory (DRFM) technology and their key role in maintaining …
Error-backpropagation-based background calibration of TI-ADC for adaptively equalized digital communication receivers
A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters
(TI-ADCs) is presented in this paper. This technique is applicable to equalized digital …
(TI-ADCs) is presented in this paper. This technique is applicable to equalized digital …
An 8-bit 800 MS/s loop-unrolled SAR ADC with common-mode adaptive background offset calibration in 28 nm FDSOI
A Akkaya, F Celik, Y Leblebici - IEEE Transactions on Circuits …, 2021 - ieeexplore.ieee.org
This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive
approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode …
approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode …
Time-and frequency-interleaving: Distinctions and connections
This paper connects the linear steady-state systematic error models of the time-and
frequency-interleaved analog-to-digital converters (ADCs). Exposing their relations is of …
frequency-interleaved analog-to-digital converters (ADCs). Exposing their relations is of …
Design and experimental verification of a novel error-backpropagation-based background calibration for time interleaved ADC in digital communication receivers
A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters
(TI-ADCs) is presented in this paper. This technique is applicable to equalized digital …
(TI-ADCs) is presented in this paper. This technique is applicable to equalized digital …
Continuous time linear equalization (CTLE) adaptation algorithm enabling baud-rate clock data recovery (CDR) locked to center of eye
ZD Wu, P Upadhyaya - US Patent 10,791,009, 2020 - Google Patents
Apparatus and associated methods relate to adapting a continuous time linear equalization
circuit with minimum mean square error baud-rate clock and data recovery circuit to be able …
circuit with minimum mean square error baud-rate clock and data recovery circuit to be able …
[图书][B] System-driven circuit design for ADC-based wireline data links
K Zheng - 2018 - search.proquest.com
In the era of connectivity, wireline I/O has been a key technology underpinning the
aggressive performance improvements of computer and communication systems. All …
aggressive performance improvements of computer and communication systems. All …
A 12.8-Gbaud ADC-based wireline receiver with embedded IIR equalizer
JW Nam, MSW Chen - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This article demonstrates an analog-to-digital converter (ADC)-based receiver for
NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle …
NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle …