While the memory bandwidth of accelerators such as GPU has significantly improved over
the last decade, the commodity networks such as Ethernet and InfiniBand are lagging in …

Fully Sharded Data Parallel (FSDP) technology achieves higher performance by scaling out
data-parallel training of Deep Learning (DL) models. It shards the model parameters …

Distributed big data in scientific computing presents a major I/O performance bottleneck
when exploiting data paral-lelism. Consumer and producer compute nodes are often …

In this work, we present DE-ZFP: a hardware implementation of modified ZFP compression
and decompression algorithms on a Field Programmable Gate Array (FPGA). It can be used …

Although neural network quantization is an imperative technology for the computation and
memory efficiency of embedded neural network accelerators, simple post-training …

HPC trends favor algorithms and implementations that reduce data motion relative to
FLOPS. We investigate the use of lossy compressed data arrays in place of traditional IEEE …

To use the CPU RAM to store the data of a GPU simulation, the data exchange between
CPU and GPU is required. With LRnLA algorithms, the computation without data exchange …

With the rapidly increasing model sizes, state-of-the-art Deep Learning (DL) models rely on
multiple GPU nodes to run distributed training. Large message communication of GPU data …

As HPC systems continue to grow to exascale, the amount of data that needs to be saved or
transmitted is exploding. To this end, many previous works have studied using error …

In recent years, many researchers have been using CPU for quantum computing simulation.
However, in reality, the simulation efficiency of the large‐scale simulator is low on a single …