A Nishida - US Patent 10,283,493, 2019 - Google Patents
A first die includes a three-dimensional memory device and first copper pads. A second die includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …
J Pachamuthu, J Alsmeier, H Chien - US Patent 9,230,987, 2016 - Google Patents
US9230987B2 - Multilevel memory stack structure and methods of manufacturing the same - Google Patents US9230987B2 - Multilevel memory stack structure and methods of …
J Liu, T Zhang, J Pachamuthu, YS Lee… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped Surfaces. First memory …
A Serov, JK Kai, Y Zhang, H Chien… - US Patent 9,728,546, 2017 - Google Patents
(57) ABSTRACT A three dimensional NAND device includes a common vertical channel and electrically isolated control gate elec trodes on different lateral sides of the channel in each …
H Kimura, S Shimabukuro, S Minagawa… - US Patent …, 2017 - Google Patents
US9576967B1 - Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings - Google Patents …
A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are …
J Pachamuthu, J Alsmeier, RS Makala… - US Patent 9,460,931, 2016 - Google Patents
(57) ABSTRACT A memory device and a method of fabricating a memory device that includes forming a protrusion over a Substrate, an etch stop layer over the protrusion, and a …