Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof

M Tsutsumi, K Kajiwara, RS Makala - US Patent 9,991,277, 2018 - Google Patents
A memory opening can be formed through an alternating stack of insulating layers and
sacrificial material layers over a substrate. A material layer stack containing, from outside to …

Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

K Miyata, Z Lu, A Lin, D Mao, J Yu, J Alsmeier… - US Patent …, 2016 - Google Patents
2016-01-13 Assigned to SANDISK TECHNOLOGIES INC. reassignment SANDISK
TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof

A Nishida - US Patent 10,283,493, 2019 - Google Patents
A first die includes a three-dimensional memory device and first copper pads. A second die
includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

KH Kim, M Higashitani, F Toyama… - US Patent 10,510,738, 2019 - Google Patents
2019-01-15 Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

Multilevel memory stack structure and methods of manufacturing the same

J Pachamuthu, J Alsmeier, H Chien - US Patent 9,230,987, 2016 - Google Patents
US9230987B2 - Multilevel memory stack structure and methods of manufacturing the same
- Google Patents US9230987B2 - Multilevel memory stack structure and methods of …

Multilevel memory stack structure employing support pillar structures

J Liu, T Zhang, J Pachamuthu, YS Lee… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A first stack of alternating layers including first electrically insulating layers
and first sacrificial material layers is formed with first stepped Surfaces. First memory …

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

A Serov, JK Kai, Y Zhang, H Chien… - US Patent 9,728,546, 2017 - Google Patents
(57) ABSTRACT A three dimensional NAND device includes a common vertical channel and
electrically isolated control gate elec trodes on different lateral sides of the channel in each …

Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings

H Kimura, S Shimabukuro, S Minagawa… - US Patent …, 2017 - Google Patents
US9576967B1 - Method of suppressing epitaxial growth in support openings and three-dimensional
memory device containing non-epitaxial support pillars in the support openings - Google Patents …

Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof

R Sharangpani, RS Makala, S Kanakamedala… - US Patent …, 2017 - Google Patents
A memory opening can be formed through an alternating stack of insulating layers and
sacrificial material layers provided over a substrate. Annular etch stop material portions are …

High aspect ratio memory hole channel contact formation

J Pachamuthu, J Alsmeier, RS Makala… - US Patent 9,460,931, 2016 - Google Patents
(57) ABSTRACT A memory device and a method of fabricating a memory device that
includes forming a protrusion over a Substrate, an etch stop layer over the protrusion, and a …