Survey of low-power testing of VLSI circuits
P Girard - IEEE Design & test of computers, 2002 - ieeexplore.ieee.org
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a
discussion of power consumption that gives reasons for and consequences of increased …
discussion of power consumption that gives reasons for and consequences of increased …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
A unified approach to reduce SOC test data volume, scan power and testing time
A Chandra, K Chakrabarty - IEEE transactions on computer …, 2003 - ieeexplore.ieee.org
We present a test resource partitioning (TRP) technique that simultaneously reduces test
data volume, test application time, and scan power. The proposed approach is based on the …
data volume, test application time, and scan power. The proposed approach is based on the …
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Y Bonhomme, P Girard, L Guiller… - … 10th Asian Test …, 2001 - ieeexplore.ieee.org
Test power is now a big concern in large system-on-chip designs. In this paper, we present a
novel approach for minimizing power consumption during scan testing of integrated circuits …
novel approach for minimizing power consumption during scan testing of integrated circuits …
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
A Chandra, K Chakrabarty - Proceedings of the 39th annual design …, 2002 - dl.acm.org
We present a test resource partitioning (TRP) technique that simultaneously reduces test
data volume, test application time and scan power. The proposed approach is based on the …
data volume, test application time and scan power. The proposed approach is based on the …
Low-transition test pattern generation for BIST-based applications
M Nourani, M Tehranipoor… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
A low transition test pattern generator, called LT-LFSR, is proposed to reduce the average
and peak power of a circuit during test by reducing the transitions among patterns …
and peak power of a circuit during test by reducing the transitions among patterns …
The dynamic granularity memory system
Chip multiprocessors enable continued performance scaling with increasingly many cores
per chip. As the throughput of computation outpaces available memory bandwidth, however …
per chip. As the throughput of computation outpaces available memory bandwidth, however …
Power driven chaining of flip-flops in scan architectures
Y Bonhomme, P Girard, C Landrault… - Proceedings …, 2002 - ieeexplore.ieee.org
Power consumption during scan testing is becoming a primary concern. In this paper, we
present a novel approach for scan cell ordering which significantly reduces the power …
present a novel approach for scan cell ordering which significantly reduces the power …
A low power pseudo-random BIST technique
NZ Basturkmen, SM Reddy, I Pomeranz - Journal of Electronic Testing, 2003 - Springer
Peak power consumption during testing is an important concern. For scan designs, a high
level of switching activity is created in the circuit during scan shifts, which increases power …
level of switching activity is created in the circuit during scan shifts, which increases power …
[图书][B] Power-constrained testing of VLSI circuits
N Nicolici, B Al-Hashimi - 2003 - Springer
Increased levels of chip integration combined with physical limitations of heat removal
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …