VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic
algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The …

Chip floorplanning is the engineering task of designing the physical layout of a computer
chip. Despite five decades of research 1, chip floorplanning has defied automation, requiring …

This paper presents a comprehensive survey on global routing research over about the last
two decades, with an emphasis on the problems of simultaneously routing multiple nets in …

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become
one of the most popular implementation media for digital circuits and have grown into a $2 …

We describe a technique for storage allocation and garbage collection in the absence of
significant co‐operation from the code using the allocator. This limits garbage collection …

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

Hybrid genetic algorithms (GAs) for the graph partitioning problem are described. The
algorithms include a fast local improvement heuristic. One of the novel features of these …

The goal of the research out of which this monograph grew, was to make annealing as much
as possible a general purpose optimization routine. At first glance this may seem a straight …

In this paper, we present FastPlace--a fast, iterative, flat placement algorithm for large-scale
standard cell designs. FastPlace is based on the quadratic placement approach. The …

This monograph represents a summary of our work in the last two years in applying the
method of simulated annealing to the solution of problems that arise in the physical design …