Techniques are disclosed for forming transistor devices hav ing source and drain regions
with high concentrations of boron doped germanium. In some embodiments, an in situ boron …

US8994104B2 - Contact resistance reduction employing germanium overlayer pre-contact
metalization - Google Patents US8994104B2 - Contact resistance reduction employing …

US7504704B2 - Shallow trench isolation process - Google Patents US7504704B2 -
Shallow trench isolation process - Google Patents Shallow trench isolation process …

A method of fabricating a semiconductor structure, in which after an etching process is
performed to form at least one recess within a semiconductor beside a gate structure, a …

2009, O124056 A1 5, 2009 Chen 2013/02998.94 A1* 11/2013 Sakuma et al...... 257,326
2009, O142931 A1 6, 2009 W. 2013/0306967 A1* 11/2013 Hoentschel et al. 257/48 tang …

Techniques are disclosed for forming column IV transistor devices having source/drain
regions with high concentra tions of germanium, and exhibiting reduced parasitic resis tance …

4,997,776 5,013,681 5,034,348 5,089,872 5,091,767 5,108,946 5,155,571 5,166,084
5,177.583 5, 198,689 5,202,284 5,207,864 5,208, 182 5,212,110 5,212,112 5,217.923 …

33AS is significantly reduce contact resistance. Numerous transistor configurations and
suitable fabrication processes will be apparent in light of this disclosure, including both …

US7420201B2 - Strained-semiconductor-on-insulator device structures with elevated source/drain
regions - Google Patents US7420201B2 - Strained-semiconductor-on-insulator device …

Structures and methods for fabricating high speed digital, analog, and combined
digital/analog systems using pla narized relaxed SiGe as the materials platform. The relaxed …