The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving
dopants from highly doped Source and drain regions by annealing for finFET devices are …

(57) ABSTRACT A process integration is disclosed for fabricating non-volatile memory
(NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate …

BACKGROUND 0002 The semiconductor integrated circuit (IC) industry has experienced
rapid growth. Technological advances in IC materials and design have produced …

Provided is a method of forming a semiconductor device. The method includes providing a
substrate having n-type doped source/drain features; depositing a flowable dielectric …

(57) ABSTRACT A semiconductor device includes a substrate including first, second, third,
and fourth regions, a first gate structure on the first region, a second gate structure on the …

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET
devices are provided. The mechanisms involve recessing fins and removing the dielectric …

(57) ABSTRACT A process integration is disclosed for fabricating complete, planar non-
volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for …

(57) ABSTRACT A Surface of a semiconductor wafer with a gate of a high dielectric constant
film formed thereon is heated to a target temperature for a short time by irradiating the …

A method is provided for fabricating an MOS transistor. The method includes providing a
semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K …

A method of manufacturing a semiconductor device includes providing a semiconductor
substrate and forming a structure over the semiconductor substrate. The structure includes a …