Fantastic Circuits and Where to Find Them-A Holistic ILP Formulation for Model-Based Hardware Design
N Fiege, P Zipf - ACM Transactions on Reconfigurable Technology and …, 2024 - dl.acm.org
The end of Moore's law and Dennard scaling emphasizes the need for application-specific
computing architectures to achieve high resource and energy efficiency and real-time …
computing architectures to achieve high resource and energy efficiency and real-time …
Design and verification of pipelined circuits with Timed Petri Nets
R Parrot, M Briday, OH Roux - Discrete Event Dynamic Systems, 2023 - Springer
A fundamental step in circuit design is the placement of pipeline stages, which can
drastically increase the data throughput. Retiming allows optimizing the pipeline with regard …
drastically increase the data throughput. Retiming allows optimizing the pipeline with regard …
Isomorphic subgraph-based problem reduction for resource minimal modulo scheduling
Modulo scheduling is a powerful method to increase throughput in high-level synthesis for
digital hardware design. When facing large designs, optimal approaches are likely to time …
digital hardware design. When facing large designs, optimal approaches are likely to time …
Réseaux de Petri temporisés pour la synthèse de circuits pipelinés
R Parrot - 2022 - theses.hal.science
Dans cette thèse, nous nous intéressons à l'optimisation des ressources consommées par
un circuit implémentant une loi de commande pour la charge de véhicules électriques sur …
un circuit implémentant une loi de commande pour la charge de véhicules électriques sur …