Computer Architecture: Complexity and Correctness develops, at the gate level, the
complete design of a pipelined RISC processor with delayed branch, forwarding, hardware …

The interlock and forwarding logic is considered the tricky part of fully-featured piplined
microprocessor and especially debugging these parts delays the hardware design process …

Subject of this thesis is the formal verification of pipelined microprocessors. This includes
processors with state of the art schedulers, such as the Tomasulo scheduler and …

We present a method of describing microprocessors at different levels of temporal and data
abstraction, and consider pipelined and superscalar processors. We model microprocessors …

Derivation and verification represent alternate approaches to design. Derivation aims at
deriving a" correct by construction" design while verification aims at constructing a post …

We extend a set of algebraic tools for representing microprocessors to model superscalar
microprocessor implementations, and apply them to a case study. We develop existing …

We apply algebraic tools for modelling microprocessors to the specification, implementation,
and verification of an abstract pipelined case study. We employ a model of time based on …

This paper presents how to generate the implementation of a pipelined microprocessor from
an arbitrary sequential specification. All necessary forwarding and stalling logic is created …

We show that the programming model of delayed branch is equivalent to what we call
delayed PC: all instruction fetches are delayed by one instruction, not just taken branches …

The data and temporal abstractions of a pipelined case study are explored in an algebraic
setting. We apply a set of algebraic tools for modelling microprocessors to the specification …