Super-resolution through neighbor embedding

H Chang, DY Yeung, Y Xiong - Proceedings of the 2004 IEEE …, 2004 - ieeexplore.ieee.org
In this paper, we propose a novel method for solving single-image super-resolution
problems. Given a low-resolution image as input, we recover its high-resolution counterpart …

{MIRAGE}: Mitigating {Conflict-Based} Cache Attacks with a Practical {Fully-Associative} Design

G Saileshwar, M Qureshi - 30th USENIX Security Symposium (USENIX …, 2021 - usenix.org
Shared caches in processors are vulnerable to conflict-based side-channel attacks, whereby
an attacker can monitor the access pattern of a victim by evicting victim cache lines using …

Personalized route recommendation using big trajectory data

J Dai, B Yang, C Guo, Z Ding - 2015 IEEE 31st international …, 2015 - ieeexplore.ieee.org
When planning routes, drivers usually consider a multitude of different travel costs, eg,
distances, travel times, and fuel consumption. Different drivers may choose different routes …

Selective cache ways: On-demand cache resource allocation

DH Albonesi - MICRO-32. Proceedings of the 32nd Annual …, 1999 - ieeexplore.ieee.org
Increasing levels of microprocessor power dissipation call for new approaches at the
architectural level that save energy by better matching of on-chip resources to application …

Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

G Semeraro, G Magklis… - … Symposium on High …, 2002 - ieeexplore.ieee.org
As clock frequency increases and feature size decreases, clock distribution and wire delays
present a growing challenge to the designers of singly-clocked, globally synchronous …

A highly configurable cache architecture for embedded systems

C Zhang, F Vahid, W Najjar - … of the 30th annual international symposium …, 2003 - dl.acm.org
Energy consumption is a major concern in many embedded computing systems. Several
studies have shown that cache memories account for about 50% of the total energy …

Optimizing replication, communication, and capacity allocation in CMPs

Z Chishti, MD Powell… - … Symposium on Computer …, 2005 - ieeexplore.ieee.org
Chip multiprocessors substantially increase capacity pressure on the on-chip memory
hierarchy while requiring fast access. Neither private nor shared caches can provide both …

Reducing set-associative cache energy via way-prediction and selective direct-mapping

MD Powell, A Agarwal, TN Vijaykumar… - … . 34th ACM/IEEE …, 2001 - ieeexplore.ieee.org
Set-associative caches achieve low miss rates for typical applications but result in significant
energy dissipation. Set-associative caches minimize access time by probing all the data …

A survey on cache tuning from a power/energy perspective

W Zang, A Gordon-Ross - ACM Computing Surveys (CSUR), 2013 - dl.acm.org
Low power and/or energy consumption is a requirement not only in embedded systems that
run on batteries or have limited cooling capabilities, but also in desktop and mainframes …

[PDF][PDF] Analytical energy dissipation models for low-power caches

MB Kamble, K Ghose - Proceedings of the 1997 international symposium …, 1997 - dl.acm.org
We present detailed analytical models for estimating the energy dissipation in conventional
caches as well as low energycacheaxchitectures. The analyticalmodelsusethenm time …