A novel approach to design SRAM cells for low leakage and improved stability

T Tripathi, DS Chauhan, SK Singh - Journal of Low Power Electronics and …, 2018 - mdpi.com
The semiconductor electronic industry is advancing at a very fast pace. The size of portable
and handheld devices are shrinking day by day and the demand for longer battery backup is …

Analysis of cache (SRAM) memory for core I™ 7 processor

R Agrawal, VK Tomar - 2018 9th international conference on …, 2018 - ieeexplore.ieee.org
This paper presents the implementation of single-bit SRAM cell architecture along with its
peripherals in standard gpdk 90nm technology library using Cadence tool. Different …

Analysis of low power reduction techniques on cache (SRAM) memory

R Agrawal, VK Tomar - 2018 9th International Conference on …, 2018 - ieeexplore.ieee.org
This paper proposes the single-bit cache memory architecture with its peripherals like write
driver circuit, a precharge circuit, SRAM Cell and Charge-Transfer Sense Amplifier. Then …

A novel design of low power & high speed FinFET based binary and ternary SRAM and 4* 4 SRAM array

N Shylashree, MS Amulya, GR Disha… - IETE Journal of …, 2023 - Taylor & Francis
The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor
(CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs) …

Low power single-bit cache memory architecture

R Agrawal, N Faujdar, A Saxena - IOP conference series …, 2021 - iopscience.iop.org
A quantitative and yield analysis of single bit cache memory architecture has been analyzed.
A single bit cache memory architecture is made up of a write driver circuit, SRAM cell, and …

Cache memory architecture for core processor

R Agrawal - Proceedings of International Conference on Advanced …, 2022 - Springer
A quantitative and yield analysis of single bit cache memory architecture has been analysed.
Single bit cache memory architecture is made up of a write driver circuit, static random …

Millimeter-scale lithium ion battery packaging for high-temperature sensing applications

N Masurkar, G Babu, S Porchelvan, LMR Arava - Journal of Power Sources, 2018 - Elsevier
Continuously growing and miniaturizing autonomous electronic devices and sensors for
large temperature window is mostly depends on stability and performance of power-up …

Design and Analysis of Low Power FinFET SRAM with Leakage Current Reduction Techniques

KS Chandra, KH Kishore - Wireless Personal Communications, 2023 - Springer
This article examines the development of a low power FINFET SRAM and applying different
techniques to reduce leakage current. Due to scalability, the CMOS parameters are not …

Analysis of cache memory architecture design using low-power reduction techniques for microprocessors

R Agrawal - … Advances in Manufacturing, Automation, Design and …, 2022 - Springer
In this paper, design analysis of single-bit cache memory architecture has been done. The
proposed single-bit cache memory architecture comprises of the write driver circuit, static …

[PDF][PDF] Design of Low Power Transmission Gate Based 9T SRAM Cell.

S Rooban, M Leela, MZ Ur Rahman… - … , Materials & Continua, 2022 - academia.edu
Considerable research has considered the design of low-power and high-speed devices.
Designing integrated circuits with low-power consumption is an important issue due to the …