A 529-μW fractional-N all-digital PLL using TDC gain auto-calibration and an inverse-class-F DCO in 65-nm CMOS
This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement
In this work, we present a compact “adaptive downsampling” method that mitigates the
nonlinearity problems associated with FPGA-based TDCs that utilize delay lines …
nonlinearity problems associated with FPGA-based TDCs that utilize delay lines …
A 0.0043-mm2 0.3–1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
This paper presents a synthesized fractional-N digital phase-locked loop (PLL) with a
speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC …
speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC …
A 5-GHz low-power low-noise integer-N digital subsampling PLL with SAR ADC PD
In this paper, we present a low-power low-noise integer-N divider-less digital phase-locked
loop (PLL) with high resolution. Phase detection is performed by a proposed analog-to …
loop (PLL) with high resolution. Phase detection is performed by a proposed analog-to …
A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction
A 50 MS/s two-step flash-MASH 1-1-1 time-to-digital converter (TDC) employing a two-
channel time-interleaved time-domain register with an implicit adder/subtractor realizes an …
channel time-interleaved time-domain register with an implicit adder/subtractor realizes an …
Adaptive spur cancellation technique in all-digital phase-locked loops
R Avivi, M Kerner, E Shumaker… - … on Circuits and …, 2017 - ieeexplore.ieee.org
The phenomenon of periodic phase errors (also known as spurs) in phase-locked loops
(PLLs) is widely acknowledged and is responsible for posing considerable challenge on …
(PLLs) is widely acknowledged and is responsible for posing considerable challenge on …
Analog/mixed-signal circuit synthesis enabled by the advancements of circuit architectures and machine learning algorithms
Analog mixed-signal (AMS) circuit architecture has evolved towards more digital friendly due
to technology scaling and demand for higher flexibility/reconfigurability. Mean-while, the …
to technology scaling and demand for higher flexibility/reconfigurability. Mean-while, the …
Realization of Zero Measurement Dead Time on FPGA-based Time-to-Digital Converters
X Qi, J Zhang, Y Wang - IEEE Transactions on Instrumentation …, 2024 - ieeexplore.ieee.org
Although the time-to-digital converters (TDCs) implemented on field programmable gate
arrays (FPGAs) have achieved considerably high measurement resolution and precision in …
arrays (FPGAs) have achieved considerably high measurement resolution and precision in …
A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator
This paper presents a jitter reduction technique for a voltage-controlled ring oscillator
(VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital …
(VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital …
Thermal and flicker phase noise analysis in rotary traveling‐wave oscillator
S Abbasalizadeh, M Javadi… - International Journal of …, 2019 - Wiley Online Library
This paper analyzes the thermally induced phase noise and the up‐conversion of flicker
noise into phase noise of rotary traveling‐wave oscillator (RTWO). Based on the analyses …
noise into phase noise of rotary traveling‐wave oscillator (RTWO). Based on the analyses …