SH Zalewski, AH Mason, GH Jordan… - US Patent 6,542,926, 2003 - Google Patents
Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The …
M Vorbach, R Münch - US Patent 7,010,667, 2006 - Google Patents
An internal bus system for DFPs and units with two-or multi-dimensional programmable cell architectures, for managing large Volumes of data with a high interconnection complexity …
TJ Van Hook, P Hsu, WA Huffman, HP Moreton… - US Patent …, 1999 - Google Patents
Today, most processors in microcomputer Systems pro vide a 64-bit wide datapath architecture. The 64-bit datapath allows operations Such as read, write, add, Subtract, and …
M Vorbach, R Münch - US Patent 6,697,979, 2004 - Google Patents
An arrangement and a method are provided for replacing defective units, which can be any desired unit of a chip (eg, arithmetic and logic units), with a function unit. The arrangement …
AC Felch, RH Granger - US Patent 8,200,992, 2012 - Google Patents
This invention provides a computer system architecture and method for providing the same which can include a web page search node including a web page collection. The system …
A Sazegari - US Patent 7,337,205, 2008 - Google Patents
To perform multiplication of matrices in a vector processing system, partial products are obtained by dot multiplication of vector registers containing multiple copies of elements of a …
M Vorbach, R Münch - US Patent 7,565,525, 2009 - Google Patents
(57) ABSTRACT A cascadable arithmetic and logic unit (ALU) which is con figurable in function and interconnection. No decoding of commands is needed during execution of the …
M Vorbach, R Münch - US Patent 6,477,643, 2002 - Google Patents
(57) ABSTRACT A method for processing data in a configurable unit having a multidimensional cell arrangement a Switching table is provided, the Switching table …
M Vorbach, A Thomas - US Patent 8,812,820, 2014 - Google Patents
(57) ABSTRACT A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a? rst clock rate and …