Comparator power minimization analysis for SAR ADC using multiple comparators

M Ahmadi, W Namgoong - … on Circuits and Systems I: Regular …, 2015 - ieeexplore.ieee.org
Comparator power consumption is a major bottleneck to the power efficiency of a high
resolution successive approximation register (SAR) analog-to-digital converter (ADC) used …

A two-step prediction ADC architecture for integrated low power image sensors

H Yu, W Tang, M Guo, S Chen - IEEE transactions on circuits …, 2016 - ieeexplore.ieee.org
This paper presents a two-step prediction method for the design of low-power column-
parallel analog-to-digital converters (ADC) in CMOS image sensors. The proposed …

A historical perspective on hardware AI inference, charge-based computational circuits and an 8 bit charge-based multiply-add core in 16 nm FinFET CMOS

KA Sanni, AG Andreou - … on Emerging and Selected Topics in …, 2019 - ieeexplore.ieee.org
The second wave of AI is about statistical learning of low dimensional structures from high
dimensional data. Inference is done using multilayer, data transforming networks using fixed …

Real Number Modeling of a SAR ADC behavior using SystemVerilog

C Sapsanis, M Villemur… - 2022 18th International …, 2022 - ieeexplore.ieee.org
The advances in fabrication technology increase complexity of integrated circuits (ICs)
achieving even higher integration. Modern ICs encompass multiple analog, mixed-mode …

A 3.3 fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation

M Ahmadi, W Namgoong - … of the IEEE 2013 Custom Integrated …, 2013 - ieeexplore.ieee.org
This paper presents a 10b successive approximation register (SAR) analog-to-digital
converter (ADC) that operates at 0.5 V supply voltage and supports a flexible differential …

Ultra low energy analog image processing using spin based neurons

M Sharad, C Augustine, G Panagopoulos… - Proceedings of the 2012 …, 2012 - dl.acm.org
In this work we present an ultra low energy,'on-sensor'image processing architecture, based
on cellular network of spin based neurons. The'neuron'constitutes of a lateral spin valve …

Comparator power reduction in low-frequency SAR ADC using optimized vote allocation

M Ahmadi, W Namgoong - … on very large scale integration (VLSI …, 2014 - ieeexplore.ieee.org
When operating at scaled supply voltages, the primary source of performance degradation
in a successive approximation register (SAR) analog-to-digital converter (ADC) is the …

Predictive Sampling in Image Sensing for Sparse Image Processing

A Biglari, Q Hu, W Tang - IEEE Sensors Letters, 2024 - ieeexplore.ieee.org
This paper presents a pixel-level predictive sampling method for image sensing and
processing to reduce the computing overhead for power-limited image sensing systems. The …

A low-cost tiny-size successive approximation ADC for applications requiring low-resolution conversion with moderate sampling rate

H Aminzadeh - Circuits, Systems, and Signal Processing, 2019 - Springer
The required silicon die area of successive approximation analog-to-digital converters (SA-
ADCs) increases rapidly with ADC resolution. In particular, a main design challenge for SA …

[PDF][PDF] Time-Delay-Integration CMOS Image Sensor Design For Space Applications

Y Hang - School of Electrical and Electronic Engineering, a …, 2016 - personal.ntu.edu.sg
In recent years, remote imaging systems have been used for a wide range of applications in
geological exploration, oceanography, meteorology, military reconnaissance, etc. Differing …