A successive approximation register (SAR)-assisted digital-slope analog-to-digital converter
(ADC) with an “8-bit+ 4-bit” hybrid topology is presented. In the coarse quantization with an 8 …

This paper presents a high-speed common-mode insensitive two-stage regenerative
comparator designed for low supply voltage applications. The proposed comparator features …

The article addresses a novel topology of analog voltage comparator capable of processing
the input voltage in rail-to-rail range. We propose two different innovative comparator …

A dynamic latched comparator with a programmable tail transistor is proposed. The tail
transistor is divided into N branches that could be enabled or disabled to allow optimizing …

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low
power consumption is introduced. The comparator can be employed in low-power …

In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage
operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) …

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and
split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 …

Dynamic comparators are an essential part of low-power analog to digital converters (ADCs)
and are referred to as one of the most important building blocks in mixed mode circuits. The …

Localized data conversions for sensors placed under harsh environmental conditions often
require Analog to Digital Converters (ADC) capable of working under wide operating …

It is an attractive feature to make the capacity of power storage as small as possible in
battery-free devices, while it may cause task failure frequently because of its unsatisfactory …