The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …

This paper reviews soft error rate (SER) mitigations with standard process modifications in
up-to-date commercial CMOS SRAMs and flip-flops. Acting in the front-end or middle-end …

Multi-bit upset (MBU) events collected from accelerated soft error rate (SER) measurements
performed with a quasi-monoenergetic neutron beam were analyzed with a threefold …

Neutron and alpha SER test results are presented for two SRAMs processed in a
commercial 65 nm CMOS technology. Devices with the commonly used triple well option …

There is an invisible enemy that constantly threatens the operation of electronics: ionizing
radiation. From sea level to outer space, ionizing radiation is virtually everywhere. At sea …

Soft error rates for triple-well and dual-well SRAM circuits over the past few technology
generations have shown an apparently inconsistent behavior. This work compares the …

Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The
contribution of single and multiple cell upsets are discussed as a function of the LET for …

Radiation-induced multiple event transients (METs) are expected to become more frequent
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …

Space applications, nuclear physics, military operations, medical imaging, and especially
electronics (modern silicon processing) are obvious fields in which radiation damage can …

Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of
various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI) …