Design of MCML Based Logic for Low Power Digital Communication Application
Delay reduces the speed of operation in high-speed integrated circuits (ICs). The major
disadvantage of conventional CMOS logic is slower operation and higher energy …
disadvantage of conventional CMOS logic is slower operation and higher energy …
An Energy-efficient Method of Distributing Clock signals for System-on-Chip (SoC) using Current-mode Technique
Today's microprocessors use millions of transistors to process high-complexity data at clock
frequencies of several gigahertz. The low power clock distribution operation is essential to a …
frequencies of several gigahertz. The low power clock distribution operation is essential to a …