An exhaustive approach to detecting transient execution side channels in RTL designs of processors

MR Fadiheh, A Wezel, J Müller… - IEEE Transactions …, 2022 - ieeexplore.ieee.org
Hardware (HW) security issues have been emerging at an alarming rate in recent years.
Transient execution attacks, such as Spectre and Meltdown, in particular, pose a genuine …

Fault attacks on access control in processors: Threat, formal analysis and microarchitectural mitigation

ALD Antón, J Müller, MR Fadiheh, D Stoffel… - IEEE Access, 2023 - ieeexplore.ieee.org
Process isolation is a key component of the security architecture in any hardware/software
system. However, even when implemented correctly and comprehensively at the software …

Design of Access Control Mechanisms in {Systems-on-Chip} with Formal Integrity Guarantees

D Mehmedagić, MR Fadiheh, J Müller… - 32nd USENIX Security …, 2023 - usenix.org
Many SoCs employ system-level hardware access control mechanisms to ensure that
security-critical operations cannot be tampered with by less trusted components of the …

Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL

T Jauch, A Wezel, MR Fadiheh… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
Spectre and Meltdown attacks proved Transient Execution Side Channels to be a notable
challenge for designing secure microarchitectures. Various countermeasures against these …

A scalable formal verification methodology for data-oblivious hardware

L Deutschmann, J Müller, MR Fadiheh… - … on Computer-Aided …, 2024 - ieeexplore.ieee.org
The importance of preventing microarchitectural timing side channels in security-critical
applications has surged in recent years. Constant-time programming has emerged as a best …

The scale4edge risc-v ecosystem

W Ecker, P Adelt, W Mueller… - … , Automation & Test …, 2022 - ieeexplore.ieee.org
This paper introduces the project Scale4Edge. The project is focused on enabling an
effective RISC-V ecosystem for optimization of edge applications. We describe the basic …

MCU-Wide Timing Side Channels and Their Detection

J Müller, AL Duque Antón, L Deutschmann… - Proceedings of the 61st …, 2024 - dl.acm.org
Microarchitectural timing side channels have been thoroughly investigated as a security
threat in hardware designs featuring shared buffers (eg, caches) and/or parallelism between …

A New Security Threat in MCUs--SoC-wide timing side channels and how to find them

J Müller, ALD Antón, L Deutschmann… - arXiv preprint arXiv …, 2023 - arxiv.org
Microarchitectural timing side channels have been thoroughly investigated as a security
threat in hardware designs featuring shared buffers (eg, caches) and/or parallelism between …

Hardware Mitigation and Verification For Rogue In-Flight Data Load Attacks

N Mathure, SK Srinivasan, KK Ponugoti… - 2023 30th IEEE …, 2023 - ieeexplore.ieee.org
Rogue In-Flight Data Load (RIDL) is a microarchitecture security attack that exploits store-to-
load forwarding in the line fill buffer. Several microarchitecture-level mitigations have been …

Formal Verification Techniques for Microprocessor Security

N Mathure - 2024 - search.proquest.com
Microprocessor security is a pressing concern in our rapidly evolving digital systems, where
vulnerabilities can lead to a catastrophic consequences. Recent transient execution attack …