This paper reviews the different stressor techniques used in microelectronics, in the scope of
the Ultra-Thin Body & Buried Oxide Fully-Depleted Silicon On Insulator technology (UTBB …

Abstract Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio
(Height/Width= 82.9 nm/8.6 nm) have been developed after integrating a 14 Å nitrided gate …

High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate
length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs …

This chapter reviews the major issues facing conventional complementary metal–oxide–
semiconductor (CMOS) scaling. It also discusses the basics of a fully depleted device …

Strained SOI (SSOI) n-channel trigate FinFET is designed with asymmetrically doped
stacked channels along the fin height. The OFF current is reduced with respect to lightly …

The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA
transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio …

Conventional planar transistors have been used throughout the semiconductor industry for
the past several decades. Further miniaturization of conventional devices has been proven …

We are in the era of mobile computing with smart handheld devices and remote data storage
“in the clouds.” With devices almost always on and driven by needs such as data …

This chapter explores advances in top-down semiconductor nanowires as nanoelectronics
devices. It introduces basic nanowire field-effect transistor structures developed for …

A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure
wrapping around the nanosheets. The nanosheets extend in a first direction above a …