Fast unified floorplan topology generation and sizing on heterogeneous FPGAs

P Banerjee, S Sur-Kolay… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to
the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and …

Floorplanning in modern FPGAs

P Banerjee, S Sur-Kolay… - … Conference on VLSI …, 2007 - ieeexplore.ieee.org
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and
Multiplier blocks which can host fairly large designs. While their physical design calls for …

[PDF][PDF] A comparison of heuristics for FPGA placement

S Areibi, X Bao, G Grewal, D Banerji… - … international journal of …, 2006 - researchgate.net
Abstract Field-Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that
contain configurable logic and interconnect to provide a means for fast prototyping and also …

FPGA placement using space-filling curves: Theory meets practice

P Banerjee, S Sur-Kolay, A Bishnu, S Das… - ACM Transactions on …, 2009 - dl.acm.org
Research in VLSI placement, an NP-hard problem, has branched in two different directions.
The first one employs iterative heuristics with many tunable parameters to produce a near …

[PDF][PDF] Meta-Heuristic Based Techniques for FPGA Placement: A Study.

S Areibi, X Bao, G Gréwal, DK Banerji… - Int. J. Comput. Their …, 2009 - academia.edu
A key advantage of Field-Programmable Gate Arrays (FPGAs) over full-custom and semi-
custom devices is that they provide relatively quick implementation from concept to physical …

Faster placer for island-style FPGAs

P Banerjee, S Sur-Kolay - 2007 International Conference on …, 2007 - ieeexplore.ieee.org
In this paper, we propose a placement method for island-style FPGAs, based on fast yet very
good initial placement followed by refinement using ultra-low temperature simulated …

Improving FPGA placement with a self-organizing map

T Bostelmann, S Sawitzki - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
This work shows how the results of netlist placement for island style FPGAs can be improved
by the use of a self-organizing map. The structural information of a netlist is used to generate …

Wirelength-driven force-directed 3D FPGA placement

W Sui, S Dong, J Bian - Proceedings of the 20th symposium on Great …, 2010 - dl.acm.org
In this paper, a wirelength-driven force-directed three-dimension (3-D) Field Programmable
Gate Arrays (FPGA) placement algorithm (3D-WFP) is presented. The algorithm is …

[PDF][PDF] Improving FPGA-placement with a self-organizing map accelerated by GPU-computing

T Bostelmann, P Kewisch, L Bublies… - … Journal On Advances …, 2017 - personales.upv.es
Programmable circuits and, nowadays, especially fieldprogrammable gate arrays (FPGAs)
are widely applied in computationally demanding signal processing applications …

力驱动三维FPGA 布局算法

隋文涛, 董社勤, 边计年 - 计算机辅助设计与图形学学报, 2011 - jcad.cn
三维FPGA 布局问题的复杂度与二维情况相比成指数倍增长, 布局算法需要花费大量时间,
影响了FPGA 物理设计效率. 为了在保证布局质量的前提下缩短布局时间 …