In this paper, the impact of scaling on the gate all around the nanosheet field effect transistor
(GAA NSFET) is assessed in detail at sub-5-nm nodes for digital and analog/RF …

Recently, increasing power leakage has become a major concern especially in MOSFET
based nanoscale devices due to poor gate control. To mitigate these problems, the devices …

A compact Lambert W function-based model is proposed to analyze the drain current of
three different fin-shaped Trigate (TG) FinFETs, namely rectangular (RE_TG), trapezoidal …

This article proposes an analytical model for channel potential and threshold voltage for
negative capacitance junctionless FinFET (NC-JL FinFET). The Poisson's equation has …

The increasing demand of portable gadgets for emerging VLSI applications call for the low
power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell …

In this paper, for the first time, the performance of 3D Nanosheet FETs (NSFETs) is reported
in the inversion (INV), accumulation (ACC), and junctionless (JL) modes at elevated …

In this article, an analytical Subthreshold Drain Current model has been developed for
Negative Capacitance Junctionless FinFET (NC-JL FinFET). To obtain the subthreshold …

This work presents the design and simulation of a novel double-gate L-shaped Schottky
barrier MOSFET (DG-LS-SB-MOSFET). The device uses a low work function metal near …

This paper reports a thorough investigation of the impacts of a spacer dielectric on the
performance of HfO 2-ferroelectric-based negative capacitance (NC)-FinFETs for 10 nm …

The gate-induced drain leakage (GIDL) current is one of the important short channel effects.
It is very significant to study the GIDL current (I GIDL) in negative capacitance-based FETs …