A low-power comparator is presented. pMOS transistors are used at the input of the
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the
voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in …

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS
transistors are used at the input of the first and second stages of the comparator. At the …

A low‐power technique to reduce the power consumption of the dynamic comparators is
presented. Using this technique, the pre‐amplification phase of the comparator is stopped …

In this paper, a method is presented to reduce the power consumption of the two-stage
dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier …

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐
type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the …

In this paper, a two-stage dynamic comparator circuit is proposed, which considerably
reduces the power consumption as well as the power-delay product parameter, while …

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this
method, the SACs are modeled as a discrete time system. Unlike previous methods, the …

A foreground calibration technique for high-resolution, high-speed R-2R ladder-based
current-steering digital-to-analog converter (DAC) is proposed. This kind of converter suffers …

This paper introduces a fully-differential current steering, dynamically performance tunable
digital-to-analog converter (DPT-DAC) for 5G and 6G telecommunication systems. In the …