A 2-D multiple transform processor for the versatile video coding standard
Versatile video coding (VVC) will be the next generation video coding standard, which is
expected to replace HEVC in CE devices, such as tablets, smartphones, and TV sets beyond …
expected to replace HEVC in CE devices, such as tablets, smartphones, and TV sets beyond …
Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms
This study presents a design of two-dimensional (2D) discrete cosine transform (DCT)
hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field …
hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field …
A high performance FPGA-based architecture for the future video coding adaptive multiple core transform
Future video coding (FVC) will be the next generation video coding standard. Yet in the first
stages of the standardization process, it is expected to replace high efficiency video coding …
stages of the standardization process, it is expected to replace high efficiency video coding …
An FPGA-based architecture for the versatile video coding multiple transform selection core
Versatile video coding (VVC) will be released by 2020, and it is expected to be the
nextgeneration video coding standard. One of its enhancements is multiple transform …
nextgeneration video coding standard. One of its enhancements is multiple transform …
Smart lossy compression of images based on distortion prediction
SS Krivenko, O Krylova, E Bataeva… - … and Radio Engineering, 2018 - dl.begellhouse.com
Images of different origin are used nowadays in numerous applications spreading the
tendency of world digitalization. Despite increase of memory of computers and other …
tendency of world digitalization. Despite increase of memory of computers and other …
Effective hardware accelerator for 2d dct/idct using improved loeffler architecture
Z Zhou, Z Pan - IEEE Access, 2022 - ieeexplore.ieee.org
This paper proposes an effective hardware accelerator for 2D discrete cosine transform
(DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture …
(DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture …
Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA
A Phadikar, H Mandal, TL Chiu - Multidimensional Systems and Signal …, 2020 - Springer
Dither modulation is a well-known data hiding technique for the quality access control of the
digital image. Sometimes, quality access control demands real-time hardware …
digital image. Sometimes, quality access control demands real-time hardware …
A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved BG Lee Algorithm
A 2D Discrete Cosine Transform and Inverse Discrete Cosine Transform using the BG Lee
algorithm, incorporating a signed error-tolerant adder for additions, and a signed low-power …
algorithm, incorporating a signed error-tolerant adder for additions, and a signed low-power …
Hardware efficient architecture for 2D DCT and IDCT using Taylor-series expansion of trigonometric functions
D Mukherjee, S Mukhopadhyay - IEEE Transactions on Circuits …, 2019 - ieeexplore.ieee.org
This paper presents a hardware architecture for 8 x 8 2D Discrete Cosine Transform (DCT)
and Inverse DCT (IDCT) using Taylor-series expansion of trigonometric functions. The …
and Inverse DCT (IDCT) using Taylor-series expansion of trigonometric functions. The …
FPGA based low power hardware for quality access control of compressed gray scale image
This paper proposes novel hardware architecture of passive data-hiding scheme for quality
access control of digital image in discrete cosine transform compressed domain. Both serial …
access control of digital image in discrete cosine transform compressed domain. Both serial …