In an embodiment, a system includes a memory controller, processors and corresponding
caches. The system may include sources of uncertainty that prevent the precise scheduling …

System, methods and apparatus are described that facilitate transmission of data,
particularly between two devices within an electronic apparatus. Data is selectively transmit …

BACKGROUND Unless otherwise indicated herein, the materials described in this section
are not prior art to the claims in this application and are not admitted to be prior art by …

A microprocessor implemented method for processing a load instruction is disclosed. The
method comprises computing a virtual address corresponding to the load instruction. Next, it …

The complexity of the logic of the cache coherency manager unit is reduced by leveraging
the data path for intervention messages and responses to carry data associated with …

(57) ABSTRACT A system and method for compiling or runtime executing a fork-join data
parallel program with function calls. In one embodiment, the system includes:(1) a partitioner …

A method and apparatus for providing support for self modifying guest code. The apparatus
includes a memory, a hardware buffer, and a processor. The processor is configured to …

System, methods and apparatus are described that facilitate transmission of data,
particularly between two devices within an electronic apparatus. Information is transmitted in …

A mutltiport memory cell having improved density area is disclosed. The memory cell
includes a data storing component, a first memory access component coupled to a first side …

A high speed serial interface is provided. In one aspect, the high speed serial interface uses
three phase modulation for jointly encoding data and clock information. Accordingly, the …