Germanium CMOS potential from material and process perspectives: Be more positive about germanium

A Toriumi, T Nishimura - Japanese Journal of Applied Physics, 2017 - iopscience.iop.org
CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is
expected. This size scaling will end sooner or later, however, because the typical size is …

Reconsideration of electron mobility in Ge n-MOSFETs from Ge substrate side—Atomically flat surface formation, layer-by-layer oxidation, and dissolved oxygen …

CH Lee, T Nishimura, T Tabata, C Lu… - 2013 IEEE …, 2013 - ieeexplore.ieee.org
We clarified wafer-related origins for electron mobility degradation in Ge n-MOSFETs. High-
N s electron mobility was dramatically improved thanks to (i) atomically flat Ge surface …

Step and Terrace Formation on Ge (111) Surface in H2 Annealing

T Nishimura, CH Lee, K Nagashio… - Applied Physics …, 2012 - iopscience.iop.org
This paper reports the atomically flat surface formation of germanium (Ge)(111) in hydrogen
gas (H 2) annealing. The (111)-oriented Ge substrate was annealed at 350–850 C, and the …

Mobility fluctuation-induced low-frequency noise in ultrascaled Ge nanowire nMOSFETs with near-ballistic transport

W Wu, H Wu, W Sun, M Si, N Conrad… - … on Electron Devices, 2018 - ieeexplore.ieee.org
In this paper, we study the low-frequency noise in the Ge nanowire (NW) nMOSFETs with
sub-100-nm channel length. The low-frequency noise with 1/f characteristics is proved to …

High electron mobility n-channel Ge MOSFETs with sub-nm EOT

A Toriumi, C Lee, C Lu, T Nishimura - ECS Transactions, 2014 - iopscience.iop.org
We demonstrate that Ge FETs show significantly high mobility of not only hole but also
electron. In particular, this paper discusses what challenging issues are in n-channel FETs …

Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration

K Garidis - 2020 - diva-portal.org
As the semiconductor industry moves beyond the 10 nm node, power consumption
constraints and reduction of the negative impact of parasitic elements become important …

Experimentally effective clean process to CV characteristic variation reduction of HKMG MOS devices

CH Chen, Y Li, CY Chen, YY Chen… - 2013 13th IEEE …, 2013 - ieeexplore.ieee.org
In this work, the planar HKMG MOS devices are fabricated on (100) wafer with p-substrate.
To improve the samples' interface roughness between the Si/Ge film and the interface layer …

Comparative investigation into the interface passivation of Ge n-and p-MOSFETs with various 2D materials

W Wu, Z Zheng, W Sun, S Xu, J Li… - Applied Physics …, 2019 - iopscience.iop.org
Abstract 2D materials provide an alternative way to passivate the Ge/oxide interface
because of their conduction and valence band offsets. The effectiveness of their interface …

(Keynote) Interface Control for High Performance N-Channel Ge FETs

A Toriumi - ECS Transactions, 2017 - iopscience.iop.org
We demonstrate that Ge FETs show significantly high mobility of not only hole but also of
electron. This paper discusses, in particular, what are challenging issues in n-channel FETs …

Materials and process controls for scalable and reliable germanium gate stacks

A Toriumi - 2016 13th IEEE International Conference on Solid …, 2016 - ieeexplore.ieee.org
Germanium (Ge) is not a new material but now spotlighted for beyond Si-scaled CMOS. Ge
p-MOSFETs have been well investigated and its high performance has so far been …