A survey on cache tuning from a power/energy perspective

W Zang, A Gordon-Ross - ACM Computing Surveys (CSUR), 2013 - dl.acm.org
Low power and/or energy consumption is a requirement not only in embedded systems that
run on batteries or have limited cooling capabilities, but also in desktop and mainframes …

Improving IPC in simultaneous multi-threading (SMT) processors by capping IQ utilization according to dispatched memory instructions

A Sahba, R Sahba, WM Lin - 2014 World Automation Congress …, 2014 - ieeexplore.ieee.org
Simultaneous multithreading (SMT) provides a method to improve resource uti-lization and
performance of superscalar CPUs by sharing key data-path components among multiple …

Design space exploration of cache memory—A survey

BR Upadhyay, TSB Sudarshan - … International Conference on …, 2016 - ieeexplore.ieee.org
Cache memory plays a major role in memory hierarchy for improving the system
performance. Cache configuration includes cache size, associativity, block size …

Multi-objective optimization of energy consumption and execution time in a single level cache memory for embedded systems

JD Álvarez, JL Risco-Martín, JM Colmenar - Journal of Systems and …, 2016 - Elsevier
Current embedded systems are specifically designed to run multimedia applications. These
applications have a big impact on both performance and energy consumption. Both metrics …

[PDF][PDF] On maximizing resource utilization for simultaneous multi-threading (smt) processors by instruction recalling

Y Zhang, C Douglas, WM Lin - Proceedings of the International …, 2012 - world-comp.org
Simultaneous multi-threading (SMT) has been a very popular design in improving resource
utilization by sharing key datapath components among multiple independent threads. When …

A cache tuning heuristic for multicore architectures

M Rawlins, A Gordon-Ross - IEEE transactions on computers, 2013 - ieeexplore.ieee.org
Since multicore architectures are becoming more popular, recent multicore optimizations
focus on energy consumption. In this paper, we focus on reducing the energy consumption …

Recalling instructions from idling threads to maximize resource utilization for simultaneous multi-threading processors

Y Zhang, C Douglas, WM Lin - Computers & Electrical Engineering, 2013 - Elsevier
Abstract Simultaneous Multi-Threading (SMT) has been a very popular design in improving
resource utilization by sharing key datapath components among multiple independent …

Efficient cache exploration method for a tiled chip multiprocessor

AM Dani, YN Srikant, B Amrutur - 2012 19th International …, 2012 - ieeexplore.ieee.org
Past studies use deterministic models to evaluate optimal cache configuration or to explore
its design space. However, with the increasing number of components present on a chip …

A Classification Model for Predicting Suitable Cache Level in a Multi-core Architecture

V Thasneema, S Bhaskaran - 2021 International Conference …, 2021 - ieeexplore.ieee.org
Cache memory has an important role in achieving system performance in multi-core
architecture. Finding the best suitable cache configuration for an application is a very …

Dynamic issue queue capping for simultaneous multithreaded processors

M GÜNEY, B KURU, S Sari… - Turkish Journal of …, 2021 - journals.tubitak.gov.tr
A simultaneous multithreaded (SMT) processor mixes multiple instruction streams in its
superscalar out-of-order execution core for higher throughput. To achieve this, a superscalar …