This work has been focused on designing a phase locked loop (PLL) operating in the GHz
range with reduced reference spur and power requirement suitable for wireless …

A compensated charge pump for use in phase‐locked loops (PLLs) is presented, which
reaches several of the desired design goals for this type of circuit. The measured mismatch …

A novel phase‐locked loop (PLL) architecture including a composite phase frequency
detector (PFD), two charge pumps, variable loop filter topology and voltage‐controlled …

This paper explores a speed and power improved dead zone free, low gate count CMOS
phase frequency detector with charge pump (PFD-CP) for clock and data recovery …

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-
threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new …

In this paper, a new charge pump circuit for reducing charge and discharge currents with low
power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump …

A fully integrated DC/DC converter for low‐voltage applications is presented. It is based on a
modified Dickson charge pump which exhibits improved performances by using integrated …

A low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty
cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential …

Based on 28nm CMOS process, a low current loss and high swing charge pump suitable for
high speed PLL circuit is designed and verified under 1.05 V voltage supply. by adopting a …

In this paper, a new high speed two-stage charge pump is designed for phase-locked loop
(PLL) application. In the proposed circuit, switch-based charge pump acts as the primary …