Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

The memory wall continues to limit the performance of modern out-of-order (OOO)
processors, despite the expensive provisioning of large multi-level caches and …

Value Prediction (VP) is a microarchitectural technique that speculatively breaks data
dependencies to increase the available Instruction Level Parallelism (ILP) in general …

Value Prediction was proposed to speculatively break true data dependencies, thereby
allowing Out of Order (OOO) processors to achieve higher instruction level parallelism (ILP) …

The microarchitectural state held by predictors in modern processors can leak sensitive
information. This is the first work to analyze the security of a special type of predictor, the …

Computer architecture design space is vast and complex. Tools are needed to explore new
ideas and gain insights quickly, at low effort and desired accuracy. Cycle Accurate …

Load instructions often limit instruction-level parallelism (ILP) in modern processors due to
data and resource dependences they cause. Prior techniques like Load Value Prediction …

当今的处理器性能与存储器带宽和延迟严重失衡的问题限制了计算系统的整体性能,
而存储器的性能对制程工艺不敏感, 在后摩尔时代下很难再通过集成电路制造工艺的迭代获得 …

Based on branch prediction, value prediction has emerged as a solution for problems
caused by true data dependencies in pipelined processors. While branch predictors have …

Modern context-based value predictors tightly associate recurring values with instructions
and contexts by building confidence upon them. However, when execution monotony exists …