With the continuous reduction of chip feature size, the continuation of Moore's Law becomes
increasingly difficult and heterogeneous integration has become one of the important …

As semiconductor device scaling faces a severe technical bottleneck, vertical die stacking
technologies have been developed to obtain high performance, high density, low latency …

Stacking semiconductor chips allows for increased packing density within a given footprint
and efficient communication between different functional layers of the chip, leading to higher …

The development of WBG (wide bandgap) semiconductors has put forward higher
requirements for packaging and interconnection technology. Cu sintering is widely …

This article focuses on the 3-D modeling methodology development of the wafer-to-wafer
hybrid bonding (W2W-HB) annealing process. With its successful application in a 2-stack …

In this article, low-temperature Cu–Cu bonding with the Ag passivation layer was
accomplished at 180° C for 3 min without a postannealing process. The Ag passivation layer …

An anti-oxidant Cu layer was achieved by remote mode N2 plasma. Remote mode plasma
treatment offers the advantages of having no defect formation, such as pinholes, by …

Low-temperature solderless Cu-Cu bonding is an important technology for advanced
packaging, such as fine-pitch 3-D packaging and heterogeneous integration. In this study …

This work focuses on the effect of Cu protrusion on the reliability of High Bandwidth Memory
(HBM) fabricated by wafer-to-wafer hybrid bonding (W2W-HB) process. The thermal stress …

Hybrid bonding enables the commercialization of ultra‐fine pitch high‐density 3D packages.
Cu/SiO2 hybrid bonding is the standard packing interface recently introduced in the industry …