Performance Analysis of Double Gate Hetero Junction Tunnel Fet

A Novel design of SOI based Fin Gate TFET

A Dharmireddy, SR Ijjada - 2021 2nd Global Conference for …, 2021 - ieeexplore.ieee.org
The steeper transistors with low power and fast speeds are the major issue of future
transistors. To continue the progress of new technology used a different combination of …
被引用次数：16 相关文章
[PDF] researchgate.net

WITHDRAWN: SS< 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications

A Dharmireddy, A Sharma, MS Babu, SR Ijjada - 2020 - Elsevier
Withdrawal Notice WITHDRAWN: SS< 30 mV/dec; Hybrid tunnel FET 3D analytical model for
IoT applications Ajaykumar Dharmireddy a, Avinash Sharma b, M. Sushanth Babu c …
被引用次数：13 相关文章

Design of low voltage-power: negative capacitance charge plasma FinTFET for AIOT data acquisition blocks

A Dharmireddy, SR Ijjada - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
The advancement of technological improvement are revved up to introduce the notion of
Artificial Intelligence of Things (AIOT) to eliminate human interaction in operation of the …
被引用次数：14 相关文章

Surface potential model of DM Fin TFET for steeper slope characteristics

A Dharmireddy, H Sudhakar, C Madhavarao… - AIP Conference …, 2024 - pubs.aip.org
This paper provides a surface model of a perimeter-weighted study of a double material Fin-
shape gate tunnel FET for steeper slope characteristics. The proposed double metal fin gate …
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0.7 V-20nm FinFET Technology Inverter Design for Better Log-Linear Characteristics

MVSR Ramani, SR Ijjada - Intelligent Circuits and Systems for SDG 3 … - taylorfrancis.com
Many new semiconductor devices unfolded in the interest of enhancement of transistor
density in the available silicon area. Latest electronics circuits looking towards adding more …
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