[图书][B] Algorithms and theory of computation handbook, volume 2: special topics and techniques

MJ Atallah, M Blanton - 2009 - books.google.com
This handbook provides an up-to-date compendium of fundamental computer science
topics, techniques, and applications. Along with updating and revising many of the existing …

一种嵌入可读水印的自适应盲水印算法

张冠男, 王树勋, 温泉 - 电子学报, 2005 - ejournal.org.cn
本文提出了一种基于DWT 的嵌入可读水印的自适应盲水印算法, 通过分析图像经离散小波变换
后细节子带系数的特性, 把细节子带系数的均值和方差作为水印信息的一部分来自适应地修改 …

Polygon representation in an integrated circuit layout

DC Chapman - US Patent 6,128,767, 2000 - Google Patents
An approach for representing polygons in an integrated circuit (IC) layout is provided.
Polygons are represented by one or more wires, which in turn are each represented by one …

[PDF][PDF] A physical synthesis design flow based on virtual components

F Moraes, M Robert, D Auvergne… - XV Conference on …, 2000 - researchgate.net
This paper presents a virtual library design flow for automatic layout synthesis tools. The
motivation to develop such design flow is to enable the use of static CMOS complex gates …

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability

T Iizuka, M Ikeda, K Asada - IEICE TRANSACTIONS on …, 2004 - search.ieice.org
This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell
layout synthesis problems are first transformed into SAT problems by our formulations. Our …

Physical design automation of transistor networks

AM Ziesemer Jr, R Reis - Microelectronic Engineering, 2015 - Elsevier
Integrated circuits implemented with traditional standard cell approaches use a limited set of
cells available in a library, created in advance, to generate its layout. It breaks complexity but …

Transistor placement for noncomplementary digital VLSI cell synthesis

MA Riepe, KA Sakallah - ACM Transactions on Design Automation of …, 2003 - dl.acm.org
There is an increasing need in modern VLSI designs for circuits implemented in high-
performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor …

TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework

R Fu, C Wang, B Yu, TY Ho - IEEE Transactions on Computer …, 2025 - ieeexplore.ieee.org
Standard cell libraries play a crucial role in modern VLSI design by providing pre-designed,
pre-characterized, and pre-verified building blocks to simplify the design process. However …

[PDF][PDF] Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

MA Riepe, KA Sakallah - … of the 1999 international symposium on …, 1999 - dl.acm.org
There is an increaing need in mo&m VLSI designs for circuits implemented in high-
peqonnance logic families such as Cascade Voltage Switch Logic, Pass Transistor Logic …

[PDF][PDF] Estimation of layout densities for CMOS digital circuits

F Moraes, L Torres, M Robert… - … Workshop on Power and …, 1998 - researchgate.net
The transistor density is one of the parameters to be considered for an optimal use of CMOS
process. Therefore, layout strategies have to be evaluated through metrics considering all …