DC Chapman - US Patent 6,128,767, 2000 - Google Patents
An approach for representing polygons in an integrated circuit (IC) layout is provided. Polygons are represented by one or more wires, which in turn are each represented by one …
F Moraes, M Robert, D Auvergne… - XV Conference on …, 2000 - researchgate.net
This paper presents a virtual library design flow for automatic layout synthesis tools. The motivation to develop such design flow is to enable the use of static CMOS complex gates …
T Iizuka, M Ikeda, K Asada - IEICE TRANSACTIONS on …, 2004 - search.ieice.org
This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our …
Integrated circuits implemented with traditional standard cell approaches use a limited set of cells available in a library, created in advance, to generate its layout. It breaks complexity but …
MA Riepe, KA Sakallah - ACM Transactions on Design Automation of …, 2003 - dl.acm.org
There is an increasing need in modern VLSI designs for circuits implemented in high- performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor …
R Fu, C Wang, B Yu, TY Ho - IEEE Transactions on Computer …, 2025 - ieeexplore.ieee.org
Standard cell libraries play a crucial role in modern VLSI design by providing pre-designed, pre-characterized, and pre-verified building blocks to simplify the design process. However …
MA Riepe, KA Sakallah - … of the 1999 international symposium on …, 1999 - dl.acm.org
There is an increaing need in mo&m VLSI designs for circuits implemented in high- peqonnance logic families such as Cascade Voltage Switch Logic, Pass Transistor Logic …
F Moraes, L Torres, M Robert… - … Workshop on Power and …, 1998 - researchgate.net
The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all …