Quo vadis, SLD? Reasoning about the trends and challenges of system level design

A Sangiovanni-Vincentelli - Proceedings of the IEEE, 2007 - ieeexplore.ieee.org
System-level design (SLD) is considered by many as the next frontier in electronic design
automation (EDA). SLD means many things to different people since there is no wide …

Mechanical engineering design complexity metrics: size, coupling, and solvability

JD Summers, JJ Shah - 2010 - asmedigitalcollection.asme.org
Developing objective measures for evaluating and measuring the complexity of design
would facilitate (1) empirical studies that require the use of equivalent but different design …

ABC: An academic industrial-strength verification tool

R Brayton, A Mishchenko - … Conference, CAV 2010, Edinburgh, UK, July …, 2010 - Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic
circuits appearing in synchronous hardware designs. ABC combines scalable logic …

An energy-aware model for the logic synthesis of quantum-dot cellular automata

FS Torres, R Wille, P Niemann… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Quantum-dot cellular automata (QCA) are an emerging field-coupled nanotechnology with
remarkable performance and energy efficiency. In order to enable the exploration of this …

Tinygarble: Highly compressed and scalable sequential garbled circuits

EM Songhori, SU Hussain, AR Sadeghi… - … IEEE Symposium on …, 2015 - ieeexplore.ieee.org
We introduce Tiny Garble, a novel automated methodology based on powerful logic
synthesis techniques for generating and optimizing compressed Boolean circuits used in …

Majority-inverter graph: A new paradigm for logic optimization

L Amaru, PE Gaillardon… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
In this paper, we propose a paradigm shift in representing and optimizing logic by using only
majority (MAJ) and inversion (INV) functions as basic operations. We represent logic …

FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

J Cong, Y Ding - … Transactions on Computer-Aided Design of …, 1994 - ieeexplore.ieee.org
The field programmable gate-array (FPGA) has become an important technology in VLSI
ASIC designs. In the past few years, a number of heuristic algorithms have been proposed …

[图书][B] Electronic design automation: synthesis, verification, and test

LT Wang, YW Chang, KTT Cheng - 2009 - books.google.com
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

[图书][B] Algorithms and Data Structures in VLSI Design: OBDD-foundations and applications

C Meinel, T Theobald - 1998 - books.google.com
One of the main problems in chip design is the huge number of possible combinations of
individual chip elements, leading to a combinatorial explosion as chips become more …

Debugging reinvented: asking and answering why and why not questions about program behavior

AJ Ko, BA Myers - Proceedings of the 30th international conference on …, 2008 - dl.acm.org
When software developers want to understand the reason for a program's behavior, they
must translate their questions about the behavior into a series of questions about code …