Silicide resistor in beol layer of semiconductor device and method
R Divakaruni, J Strane - US Patent App. 10/707,388, 2005 - Google Patents
0001. The present invention relates generally to semicon ductor devices, and more
particularly to a resistive metal lurgical wiring level of a Semiconductor integrated circuit and …
particularly to a resistive metal lurgical wiring level of a Semiconductor integrated circuit and …
Variable resistor structure and method for forming and programming a variable resistor for electronic circuits
A non-ablative structure and method for forming a variable resistor includes providing a
programmable resistive element including two or more different conductive materials, and …
programmable resistive element including two or more different conductive materials, and …
One-time programmable memory, integrated circuit including same, and method therefor
JW Hall, J Halamik, P Londak - US Patent 8,964,444, 2015 - Google Patents
A one-time programmable memory includes a first one-time programmable memory cell
including a fuse core having an input terminal for receiving a trim signal, an output terminal …
including a fuse core having an input terminal for receiving a trim signal, an output terminal …
Employing sense resistor as safety fuse in limited power source applications
D Korcharz, A Peker, Y Giat - US Patent 7,225,345, 2007 - Google Patents
(57) ABSTRACT A communication network utilizing Power Over Ethernet technology
including Power Sourcing Equipment (PSE) that includes a multi-purpose device that …
including Power Sourcing Equipment (PSE) that includes a multi-purpose device that …
Method for characterizing an active track and latch sense-amp (comparator) in a one time programmable (OTP) salicided poly fuse array
EG Khoury - US Patent 6,608,498, 2003 - Google Patents
A non intrusive isolation testing method for each of the positive and negative input (in+ &
in−) to each comparator in the array is provided. Isolation does not affect the read capability …
in−) to each comparator in the array is provided. Isolation does not affect the read capability …
One-time-programmable logic bit with multiple logic elements
S Paak, HJ Im, BY Ang - US Patent 7,567,449, 2009 - Google Patents
SUMMARY OF THE INVENTION A memory cell with a logic bit has a first one-time-pro
grammable (“OTP) memory element providing a first OTP memory element output and a …
grammable (“OTP) memory element providing a first OTP memory element output and a …
Electrical fuse and/or resistor structures
VS Basker, K Cheng, A Khakifirooz, J Li - US Patent 9,716,064, 2017 - Google Patents
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided.
The method includes forming metal gates having a capping material on a top surface …
The method includes forming metal gates having a capping material on a top surface …
Electrical fuse and/or resistor structures
VS Basker, K Cheng, A Khakifirooz, J Li - US Patent 9,721,885, 2017 - Google Patents
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided.
The method includes forming metal gates having a capping material on a top surface …
The method includes forming metal gates having a capping material on a top surface …
Electrical fuse and/or resistor structures
VS Basker, K Cheng, A Khakifirooz, J Li - US Patent 9,870,989, 2018 - Google Patents
2017-03-22 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
Electrically programmable polysilicon fuse with multiple level resistance and programming
SY Wu - US Patent 7,332,791, 2008 - Google Patents
SUMMARY OF THE INVENTION A principal object of the present invention is to provide an
effective and very manufacturable integrated circuit device. A further object of the present …
effective and very manufacturable integrated circuit device. A further object of the present …