Tracking address ranges for computer memory errors

JS Dodson, MA Gollub, WE Maule… - US Patent …, 2019 - Google Patents
Tracking address ranges for computer memory errors including detecting, by memory logic,
an error at a memory address, the memory address representing one or more memory cells …

Performing error correction in computer memory

JS Dodson, MA Gollub, WE Maule… - US Patent …, 2019 - Google Patents
Performing error correction in computer memory including receiving a read request targeting
a read address within the computer memory; accessing a mark table comprising a plurality …

Confirming memory marks indicating an error in computer memory

JS Dodson, MA Gollub, WE Maule… - US Patent …, 2019 - Google Patents
Confirming memory marks indicating an error in computer memory including detecting, by
memory logic responsive to a memory read operation, an error in at a memory location; …

Managing entries in a mark table of computer memory errors

JS Dodson, MA Gollub, WE Maule… - US Patent …, 2019 - Google Patents
Managing entries in a mark table of computer memory errors including identifying at least
two mark table entries as candidates for merger, wherein each mark table entry indicates an …

Memory error processing method and apparatus

Z Li, J Lou, Z Dongshu - US Patent App. 17/462,151, 2021 - Google Patents
BACKGROUND [0003] For application layer software in a server, software producers such
as SUSE and Red Hat provide technologies such as memory page offline, to ensure health …

Tracking address ranges for computer memory errors

JS Dodson, MA Gollub, WE Maule… - US Patent …, 2021 - Google Patents
Tracking address ranges for computer memory errors including detecting, by memory logic,
an error at a memory address, the memory address representing one or more memory cells …

System memory migration

CH Costa, C Perone, DR Medaglia - US Patent App. 15/747,213, 2018 - Google Patents
Examples include a system comprising a non-volatile memory and a volatile memory.
Examples resume the system to a prior state using state information stored in the non …

Debugger write interceptor

M Vecera, J Pechanec - US Patent 10,095,605, 2018 - Google Patents
Methods, systems, and computer program products are included for executing one or more
instructions of a program in a debugging session; receiving a command at a debugger, the …

Memory vulnerability mitigation

DJ Farrell - US Patent 12,086,072, 2024 - Google Patents
Vulnerabilities to physical memory, such as server dynamic random access memory (DRAM)
with error correction code (ECC) capability, can be mitigated though the use of guard pages …

Memory error handling during and/or immediately after a virtual machine migration

A Prasad - US Patent 11,544,153, 2023 - Google Patents
According to aspects of the present disclosure, systems and methods can be provided to
recover from memory errors that occur during or following a virtual machine migration …